Micron Technology Incorporated

Micron Semiconductor, Inc.

Nan Ya Technology Corporation

Micron Technoloay Inc.

Donald M Morgan

Todd A Merritt

Alan John Wilson

Sujeet V Ayyapureddi

Bryan David Kerstetter

John David Porter

Loren L McLaury

Jeffrey P Wright

Greg A Blodgett

Jongtae Kwak

Nobuo Yamamoto

Sean Stephen Eilert

Michael Amiel Shore

Huy Thanh Vo

Yasushi Matsubara

Victor Wong

Yusuke Jono

Bryce D Cook

Troy A Manning

Dean D Gans

Shubneesh Batra

Chris G Martin

Kallol Mazumder

Joseph C Sher

Simon J Lovett

William F Jones

Steven F Schicht

Mark K Hadrick

Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

Apparatuses and methods for dynamically allocated aggressor detection

A system for providing maximum row active time enforcement for memory devices is disclosed. A host device issues an activate command to activate a memory bank of a plurality of memory banks of a memory. The memory device activates the memory bank and determines whether a precharge command to close the first memory bank has been issued by the host device within a maximum threshold amount of time since issuance of the activate command. If the system determines that the precharge command has been issued by the host device within the threshold, the memory device closes the memory bank via the host-issued precharge command. If, however, the system determines that the precharge command has not been issued by the host device within the threshold, the memory device internally issues a precharge command to close the memory bank to reduce potential data loss and other harmful effects to the memory device.

Maximum row active time enforcement for memory devices

Systems, methods, and apparatuses are provided for wear leveling repair in a memory device. A host is configured to issue a wear leveling command and a repair request to a memory device configured to check source data in a memory of the memory device for errors in response to receiving the wear leveling command from the host, transfer source data in the memory of the memory device to a target page, and repair a source page if the source data includes an error. The memory device is further configured to set a new repair match if a wear leveling repair element was not consumed after receiving the repair request and flush a previous repair match before setting the new repair match if the wear leveling repair element was consumed and a physical address of an incoming repair request is associated with the wear leveling repair element.

Wear leveling repair in a memory device

Apparatus and methods for page-based soft post package repair are disclosed. Based on data stored in a storage element, an address may be decoded to a prime row, a row-based redundant row, or a page-based redundant row. A match logic circuit may determine whether the address corresponds to a defective prime row and generate a match signal. A decoder can select a redundant row to be accessed instead of a prime row in response to the match signal indicating that the address data corresponding to the address to be accessed matches defective address data stored in a volatile memory. A page-based redundant row allows for page-by-page substitution for defective memory, allowing functional portions of memory to continue to be used.

Memory device with redundancy for page-based repair

Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

Error logging for a memory device with on-die wear leveling

Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.

Managing page retirement for non-volatile memory

Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an 'ON' state). Accordingly, the value of the counter may be maintained across power cycles.

Memory row-hammer mitigation

Methods, systems, and devices for frequency regulation for memory management commands are described. A memory device may maintain a respective first counter and second counter for each monitoring area of the memory device, where the counters may be incremented for each activate command received for the corresponding monitoring area. If the first counter satisfies a first threshold, an activate command issued to the monitoring area may be ignored. If the second counter fails to satisfy a second threshold, a memory management command issued to the monitoring area may be ignored and the memory device may maintain a value of the second counter, while decrementing the first counter. Alternatively, if the second counter satisfies the second threshold, the memory device may perform a memory management operation associated with a received memory management command and may decrement the first counter and the second counter.

Frequency regulation for memory management commands

Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.

Repair operation techniques

Methods, systems, and devices for techniques for non-volatile data protection are described. As part of a power on operation, a non-volatile memory system may be configured to selectively stored data. For example, the memory system may determine whether a host system is authorized to access data stored in the memory system prior to a power off operation. If the memory system determines that the host system is authorized, the memory device may retain the data. If the memory system determines that the host system is not authorized, the memory system may erase all or a portion of the data. In some cases, the memory system may maintain a retain flag to determine whether the host system is authorized. Additionally or alternatively, the memory system may determine whether a password received from the host system is valid to determine whether the host system is authorized.

Techniques for non-volatile data protection

Methods, systems, and devices for address obfuscation for memory are described. A mapping function may map a logical address of data to a physical address of a memory cell. The mapping function may be implemented with a mapping component that includes mapping subcomponents. Each mapping subcomponent may be independently configurable to implement a logic function for determining a bit of the physical address. The mapping function may vary across memory devices or aspects of memory device, and in some cases may vary over time.

Address obfuscation for memory

Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.

Apparatuses systems and methods for automatic soft post package repair

Methods, systems, and devices for split and duplicate ripple circuits are described. A ripple circuit may be divided into stages, which may operate in parallel. For example, a first stage may have a finite number of possibilities for an output that is relevant for a second stage, and the second stages may be replicated according to the finite number of possibilities. The replicated second stages thus may operate concurrently with each other and the first stage, with each of the replicated second stages assuming a different possible output from the first stage. Once operation of the first stage is complete, the true output of the first stage may be used to select one of the second stages as corresponding to the correct assumed output, and the output of the selected second stage may be or may be included in a set of output signals for the circuit.

Split and duplicate ripple circuits

Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

Growing community of inventors

Boise, ID, United States of America

Donald M Morgan