Hewlett-packard Company

Donald M Kipp

Gregg Bernard Lesartre

Jonathan P Lotz

Samuel D Naffziger

A system for recovering most recent writer status when a mispredicted branch occurs in a processor that executes instructions out of order. A queue holds instructions stored in the order they are fetched from memory. Each slot in the queue stores a target register that will receive the results of the instruction, and a most recent writer status bit indicating whether the slot is the last instruction to write to the target register. When inserting a new instruction, each slot compares the target register of the new instruction to its target register, and when a match occurs, the slot resets its most recent writer status, and stores the new instruction slot number as a target taker. When a mispredicted branch occurs, the slot compares the mispredicted branch slot to the target taker slot, and when the target taker slot is greater, the slot regains the most recent writer status.

System for storing processor register data after a mispredicted branch

An operand dependency tracking system tracks move-to-space (MTSP) operand dependencies among instructions in a processor that executes instructions out of order. Instructions are forwarded from an instruction fetch mechanism to a reordering mechanism, where the instructions are permitted to execute out of order. After execution of an instruction by an execution unit, instructions are retired by a retire mechanism, which transforms the results of instruction execution to the architecture state. While instructions are executed in the reordering mechanism, the operand dependency tracking system detects an MTSP instruction and a load instruction. The MTSP instruction is destined to modify data in a space register that stores virtual address information. The load instruction is controlled to commence execution after the MTSP instruction commences execution. While executing the load instruction, the tracking system determines whether the load instruction is destined to use the data in the space register. When the load instruction is destined to use the data in the space register, then the tracking system performs the following steps: determines if the MTSP instruction is retired, (2) when the MTSP instruction is not retired, then aborts execution of the load instruction and repeats steps (b) and (d)(1) successively until the MTSP instruction is retired from execution; and (3) when the MTSP instruction is retired, completes execution of the load instruction. Finally, when the load instruction is not destined to use the data in the space register, then the tracking system completes execution of the load instruction regardless of when the MTSP instruction retires from execution.

Operand dependency tracking system and method for a processor that

A recovery method for each instruction in an instruction queue comprises steps of monitoring a launch bus to determine when an instruction has executed and comparing the tag number of the launched instruction with the tag numbers of the instructions upon which the instruction in the queue depends. After all dependencies for the instruction in the queue have cleared, a flag is set to indicate that the instruction is ready to launch. Even though all dependencies have cleared and the flag is set, the instruction in the queue still monitors the tag bus to check whether an instruction upon which it depends ever reexecutes. In the case that the instruction does reexecute, the instruction in the queue once again sets its flag to indicate that it is ready to launch, whereby the instruction in the queue will also reexecute. The recovery method permits the queue to operate at an optimal speed since each instruction need not wait until it is known for certain that its data will arrive before executing but rather may speculatively execute. Further, the recovery method does not require additional complex hardware but instead employs existing circuitry to monitor the reexecution of instructions.

Method and system for recovering from cache misses

A system for storing addresses of instructions being executed in a processor by storing an address of a first instruction in a line of cache or memory in an instruction address queue. With each instruction fetched from the line, the system stores an index into the instruction address queue for the entry that contains the address of the first instruction in the line. For each instruction fetched from the line, the system also stores an offset value indicating the relative position of the instruction within the line. To determine the address of an instruction, the processor uses the index to retrieve the address of the first instruction of the line from the instruction address queue, and then appends the offset value to the end of the value retrieved from the instruction address queue to form the actual memory address of the instruction.

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Fort Collins, CO, United States of America

Donald M Kipp