National Semiconductor Corporation

Texas Instruments Corporation

Donald M Archer

William David French

Constantin Bulucea

Sandeep Raj Bahl

Jeng-Jiun Yang

D Courtney Parker

Peter B Johnson

Prasad Chaparala

Richard B Merrill

Gregory J Smith

John Wendell Oglesbee

David Courtney Parker

Eric Scheuerlein

Jung S Hoei

A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors ('IGFETs'), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (, and) utilize empty wells (, and) in achieving desired transistor characteristics. Other IGFETs (, and) utilize filled wells (, and) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

Configuration and fabrication of semiconductor structure using empty and filled wells

An asymmetric insulated-gate field-effect transistor (or) has a source (or) and a drain (or) laterally separated by a channel zone (or) of body material (or) of a semiconductor body. A gate electrode (or) overlies a gate dielectric layer (or) above the channel zone. A more heavily doped pocket portion (or) of the body material extends largely along only the source. The source has a main source portion (M orM) and a more lightly doped lateral source extension (E orE). The drain has a main portion (M orM) and a more lightly doped lateral drain extension (E orE). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.

Structure and fabrication of asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions

A group of high-performance like-polarity insulated-gate field-effect transistors (, andor, and) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses

A gate electrode () of a field-effect transistor () is defined above, and vertically separated by a gate dielectric layer () from, a channel-zone portion () of body material of a semiconductor body. Semiconductor dopant is introduced into the body material to define a more heavily doped pocket portion () using the gate electrode as a dopant-blocking shield. A spacer (T) having a dielectric portion situated along the gate electrode, a dielectric portion situated along the body, and a filler portion (SC) largely occupying the space between the other two spacer portions is provided. Semiconductor dopant is introduced into the body to define a pair of source/drain portions (M andM) using the gate electrode and spacer as a dopant-blocking shield. The filler spacer portion is removed to convert the spacer to an L shape (). Electrical contacts (and) are formed respectively to the source/drain portions.

Fabrication of asymmetric field-effect transistors using L-shaped spacers

An asymmetric insulated-gate field-effect transistor () has a source () and a drain () laterally separated by a channel zone () of body material () of a semiconductor body. A gate electrode () overlies a gate dielectric layer () above the channel zone. A more heavily doped pocket portion () of the body material extends largely along only the source. Each of the source and drain has a main portion (M orM) and a more lightly doped lateral extension (E orE). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.

Asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions

An embodiment of the present invention is directed to a circuit for indicating the program status of an EPROM. The circuit includes a first and second transistor coupled to a first voltage potential. The circuit further includes a latching circuit coupled to the first and second transistors. The latching circuit outputs a first output value when the current through the first transistor is greater than the current through the second transistor and a second output value when less. The circuit further includes a capacitive element coupled between a gate of the first transistor and a third voltage potential, the capacitance of the capacitive element being such that the output of the latching circuit is always a first digital state prior to programming the EPROM and a second digital state after programming the EPROM.

Known default data state EPROM

Voltage regulators are exposed to extreme amounts of voltage over short periods of time during an electrostatic discharge (ESD) event. Shunt regulators require protection from ESD events. Capacitors are passive devices that allow current flow when not in a steady-state condition. An apparatus and method compensates for the extreme voltages inherent in ESD events. By providing capacitance across the gate-drain junction of the shunt device in combination with a gate resistor, a voltage can be applied to the gate of the active device upon commencement of an ESD event, and cause the active device to &ldquo;turn on&rdquo; The &ldquo;turned on&rdquo; active device provides a pathway for the excess voltage from the ESD event to follow and discharge so as to avoid catastrophic failures.

Apparatus and method for improving ESD and transient immunity in shunt regulators

A trim bit circuit is provided that uses a cascoded differential PMOS EPROM with a fixed offset cross-coupled latch. The output sense signal is transferred by transmission gates to NMOS latched inverters. The output is buffered by another inventor. Programming is performed by a NMOS current sink that pulls the drain of the programmed (trimmed) PMOS EPROM device to ground. This places the full positive supply across the short channel trimmed device, the punchthrough inducing a trapped charge on the device. The reference (untrimmed) PMOS EPROM device is uncharged. Thus, the two PMOS EPROM transistors have unequal current. During the read mode, a replication bias voltage is induced by an external &ldquo;read&rdquo; power-on-reset circuit, thereby placing a few volts below positive supply on the gates of the cascode devices. This allows the Vds of the PMOS EPROM devices to increase to a little less than a volt. Since the trimmed transistor has more current than the un-trimmed transistor by a few decades of current, the drain of the load latch transistor rises to a voltage limited by the saturation voltage of the EPROM devices, causing the output of the load latch device to be high.

Trim bit circuit for band-gap reference

An integrated inductor with filled etch includes a substrate of semiconductor material which includes a surface and a cavity disposed therein, a mass of dielectric material disposed within the cavity, a layer of dielectric material disposed upon the mass of dielectric material, and a patterned layer of conductive material disposed upon the layer of dielectric material, such that the integrated inductor is formed without an oxide bridge. Thus, the integrated inductor has a rugged architecture.

Integrated inductor

A rail-to-rail input common mode range differential amplifier operates on rail-to-rail voltages down to approximately one volt by utilizing one p-channel transistor to cover a first portion of the common mode range, and a second p-channel transistor to cover a second portion of the common mode range.

Rail-to-rail input common mode range differential amplifier that

An operational amplifier bias system provides input offset voltage trim current with minimum offset thermal drift. The bias system includes a bias generator that provides bias current to the op amp. Correction circuitry responsive to the bias current provides an input offset trim current that compensates for offset drift error with change in temperature. The correction circuitry includes a resistive element, an input current mirror responsive to the bias current for providing a reference current to the resistive element to provide a temperature coefficient conversion current having a predetermined temperature coefficient, and a voltage reference that sets the resistance of the resistive element.

Trim correction circuit with temperature coefficient compensation

An improved current source having high output impedance, low saturation voltage, and less sensitivity to process parameters is achieved by having enhancement P-channel transistor devices used as current mirror, while depletion P-channel transistor devices are provided as the cascode devices. A 'diode connected' depletion device may be inserted between the enhancement gate and the drain of the current reference transistor to reduce saturation voltage. The 'diode connected' depletion device keeps the drains of the enhancement devices at a similar voltage even when the enhancement and depletion device threshold, i.e. V.sub.T, do not track over temperature or process. Thus, the current mirror circuit provides not only higher output impedance, lower saturation voltage, but is also less sensitive to process variation.

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Santa Clara, CA, United States of America

Donald M Archer