International Business Machines Corporation

Cadence Design Systems, Inc.

Donald Lawrence Wheater

Michael Richard Ouellette

David E Lackey

Howard L Kalter

Jeffrey H Dreibelbis

Brion L Keller

Darren Lane Anand

Steven Frederick Oakland

John Robert Goss

Gary Douglas Grise

Erik A Nelson

Thomas E Obremski

Peter O Jakobsen

William R Corbin

Raymond J Bulaga

Claude Louis Bertin

William R Tonti

Kerry Bernstein

Wayne Frederick Ellis

Peter Juergen Klim

Wayne John Howell

Christopher McCall Durham

Erik L Hedberg

Kevin William Gorman

Paul David Kartschoke

H Bernhard Pogge

Thomas Gregory Sopchak

Pamela Sue Gillis

Emory D Keller

Bernd K Koenemann

Laura S Chadwick

Toshiharu Saitoh

John E Barth

Jerome L Cann

Michael L Combs

George S Prokop

Douglas R Firth

Brooks A Cummings

John L Harris

John Edward Barth, Jr

Anne Elizabeth Gattiker

Krishnendu Mondal

Larry Wissel

Gary William Maier

Mark Steven Styduhar

Phillip J Nigh

Timothy J Koprowski

Jody John Van Horn

Matthew Sean Grady

Mark R Taylor

Carl Frederick Barnhart

Ronald J Prilik

Robert W Bassett

Frank O Distler

Yotaro Mori

L Owen Farnsworth

Bruce Cowan

Andrew Ferko

Kevin William McCauley

Leo A Noel

Thomas James Snethen

Leonard O Farnsworth, Iii

Francis Woytowich

Robert Edward Shearer

Rex Ngo Kho

David John Iverson

David V Gangl

Brian Robert Kessler

Steven P Koch

L Owen Farnsworth, Iii

Christina L Newman

John Stuart Parenteau, Jr

William J Thibault

John K Masi

Patrick W Miller

Peter O Jacobsen

Bernd K F Koenemann

Bernd K F Koenermann

Thomas O Sopchak

A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

Test structure and methodology for three-dimensional semiconductor structures

Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

Microcontroller for logic built-in self test (LBIST)

A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. Cbonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a Ccarrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.

Diagnostic method and apparatus for non-destructively observing latch data

A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.

Structure for system for and method of performing high speed memory diagnostics via built-in-self-test

A system and method for performing high speed memory diagnostics via built-in-self-test (BIST). A test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method includes presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm, performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.

System and method for performing high speed memory diagnostics via built-in-self-test

An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits. The stimulus busses can also be used to provide each chip with parallel serial scan data as well as power and other signals such as clock and enable and disable signals. Each chip control circuit provides the chip with power, bus clock, control, enable and response lines, can also connected to each chip via suitable lines in the kerfs.

Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer

A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

Method for testing embedded DRAM arrays

A method and system for reducing test data volume in the testing of logic products such as integrated circuit chips. Test data loaded by a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises 'care' bits and 'non-care' bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. According to the invention, non-care bits in the test vector data are filled with repetitive background data to provide for a high degree of compressibility of the test vector data. A substantial portion of the care bits may also be set to a repetitive value and the original values later recovered.

Method and system for reducing test data volume in the testing of logic products

Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test algorithm is introduced to enable and disable the scan chain operation during BIST operation.

Testing logic and embedded memory in parallel

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Hinesburg, VT, United States of America

Donald Lawrence Wheater