Motorola Corporation

Freescale Semiconductor,inc.

Other

Donald L Tietjen

Frank C Galloway

Charles E Nuckolls

Terry L Biggs

Kristen L Mason

David M Menard

Jesse R Wilson

Gary R Morrison

Pern Shaw

Nancy G Woodbridge

Michael W Cruess

Jennifer L McKeown

Ronny L Arnold

Jeffrey M Polega

Juan Guillermo Revilla

Alfred Larry Crouch

Michael F Wiles

David A Hayner

Stanley E Groves

Colin MacDonald

Robert Bradford Cohen

Teresa Louise McLaurin

Alan Joseph Carlin

Paul D Shannon

Van B Shahan

Michael Alan Mateja

Michael Deur

Tulley M Peters

John Michael Hudson

Duane W Cawthron

Sanjay Patel

Sharon Lamb

A method and system for transmitting binary-coded data use partitioning of data words in a plurality of data nibbles. The data nibbles are coded using modified a 1-bit hot coding format that transforms a data nibble in a data segment including a plurality of bit groups. A change in a digital state at a bit position in a more significant bit group is maintained at that bit position in less significant bit groups, and information is transmitted in a form of a transition between digital states. The data segments are transmitted in phases each including one bit group from each data segment. At a receiving terminal, the bit groups are converted back in the binary-coded data words. In one application, the invention is used to reduce power consumption during data transmissions to and from an integrated circuit device.

Method and system for transmitting data

A method and apparatus for interconnecting circuit portions () within a data processing system () using a master/slave interfaces () which may be configured by way of configuration registers (). External address generation circuitry () and internal address generation circuitry () may be used to generate externally used addresses and internally used addresses, respectively. A circuit portion (e.g.) may have a plurality of interfaces () which may operate as a slave interface (e.g.) or as a master interface (e.g.). A same master/slave interface structure and protocol (e.g.) may be duplicated and individually configured to be used to communicate among all of the circuit portions () within a data processing system ().

Method and apparatus for interconnecting portions of circuitry within a data processing system

A programmable clock generator ( ), which is part of an integrated circuit (IC) ( ), provides clock signals ( ) and ( ) to various components of the IC. The clock generator includes a PLL ( ) and one or more choppers ( ) which provide a desired waveform to the IC for testing purposes. When used in conjunction with a tester ( ), the IC can be scan tested at-speed using slower and less expensive testing equipment.

Method and apparatus for testing an integrated circuit

Direct memory access controller (DMAC) ( ) adapted to directly execute C language style FOR tasks assigned by a processor ( ), where the FOR task includes a movement of a data element from a first location to a second location in memory. The DMAC includes multiple execution units (EUs) ( ), each to perform an arithmetic or logical operation, and a FOR task controller ( ) to perform the data movement. The FOR task controller selects the operation to be performed by the EU. In one embodiment, the FOR task is made up of C language type FOR loops, where descriptors identify the control and body of the loop. The descriptors identify the source of operands for an EU, and the source may be changed within a FOR task. A descriptor specifies a function code for an EU and may specify multiple sets of operands for the EU.

Direct memory access controller and method therefor

Direct memory access controller (DMA) ( ) adapted to directly execute C language style FOR tasks, where the FOR task includes a movement of a data element from a first location to a second location in memory, and the movement is controlled by a master DMA engine (MDE) ( ). A master DMA engine (MDE) ( ) includes a top level state machine ( ) to coordinate a context save state machine ( ), a parse state machine ( ), and a running state machine ( ). An loop control descriptor (LCD) queue ( ) and a data routing descriptor (DRD) cache store information. The LCD queue allows pipelining of descriptor parsing, while the DRD cache avoids refetching of DRDs on reentry of loops.

A data processing system (10) and method is used to recover a CPU from faulty operation. A single timer (38) is used to enable recovery operations. When the timer (38) experiences a first time-out event, a software watchdog interrupt (28) is generated. If the software interrupt (28) is properly handled before another consecutive/subsequent watchdog time out occurs, normal software execution will resume. However, if the software watchdog interrupt is not processed and the watchdog timer (38) experiences a second time-out event while the watchdog time-out interrupt (28) is pending, the timer (38) will generate a bus transfer termination signal (30) and set a status bit (270) within a watchdog status register (44). This assertion of termination signal (30) and the setting of the bit (270) allows the microprocessor to determine that a locked bus state exists. In response to the signal (30) and the bit (270), the locked bus (one or more of busses 22, 24, and/or 26) will attempt to recover from the locked bus state.

System and method for recovering a microprocessor from a locked bus state

When a processor (102) issues a request for an address (502), a determination is made as to whether or not the address is contained within a buffer (103) or cache associated with the processor (102), or the address is contained within a line of data currently being fetched from an external memory system (105). If the address is not contained within the buffer or cache and is not contained within a line being currently fetched, the current fetch will be cancelled (515, 516).

Method for canceling partial line fetch for cache when new data is

A synchronous memory interface feeds back a buffered (34) clock signal to a microcontroller (20) to simplify and improve output hold time for the memory (38). An output delay circuit (36) in the microcontroller (20) is controlled by the same delayed clock signal as the synchronous memory (38). This delay circuit (36) selectively delays memory signals to the synchronous memory (38) from the microcontroller delay circuit (36). The use of flip-flops (40, 44) in the delay circuit (36) provides a mechanism for scan testing. This enables three different selectable modes of operation of the delay circuit (36) providing flexibility in interfacing in different environments.

Synchronous memory interface

A bus interface unit within a processor ensures a delay period after the occurrence of a read operation to avoid bus contention on a multiplexed bus, When there is a requirement for a back-to-back read or write operation subsequent to the read bus cycle on a multiplexed bus it is important to allow devices, such as memory, sufficient time to reset after transmission of data. To avoid the bus contention problem that occurs after a read bus cycle, i.e, prevent a next address on the bus until the bus is in a tri-state condition, one embodiment inserts idle clock cycles subsequent to a read but not subsequent to a write, The present invention avoids bus contention on a multiplexed bus while providing flexibility in interfacing with a variety of memory devices, and providing a flexible processor design.

System and method for avoiding bus contention on a multiplexed bus by

Circuitry is implemented within an integrated circuit ('chip') (101) which is an IEEE 1149.1 compliant device capable of performing JTAG testing (104), such as an EXTEST or CLAMP testing procedure. Upon exiting of either of these procedures, the input/output pins (210) of the chip are placed in a known state, which may be a high impedance state.

Data processing system for performing a test function and method therefor

A data processing system (10) having a bus controller (5) that uses a communication bus (22) which adapts to various system resources (7) and is capable of burst transfers. In one embodiment, the processor core (2) and system resources (7) supply control signals supplying required parameters of the next transfer. The bus controller is capable of transferring operands and/or instructions in incremental bursts from these system resources. Each transfer data burst has an associated unique access address where successive bytes of data are associated with sequential addresses and the burst increment equals the data port size. The burst capability is dependent on the ability of system resource (7) to burst data and can be inhibited with a transfer burst inhibit signal. The length of the desired data is controlled by a sizing signal from the core (2) or from cache and the increment size is supplied by the resource (7).

Method and apparatus for bursting operand transfers during dynamic bus

A data processing system (10) having a bus controller (5) and a multiplexed communication bus (22) and provides a portion of the valid address information during the data phase. In one embodiment, in response to an address extension control signal, the bus controller (5) allocates the communication bus (22) to provide the address extension on conductors not needed for data, reducing the need for address latch circuitry. In an alternate embodiment, the bus controller (5) provides burst transfers where the processor core (2) increments a portion of each address with each data in the burst. For such burst transfers, the length of the desired data is controlled by a sizing signal (42) from the core (2) or from cache and the increment size is supplied by the system resource (7).

Method and apparatus for address extension across a multiplexed

A method and apparatus for providing both power and control by way of an integrated circuit terminal (22). In one form, a clock source (12) supplies a periodic signal to a phase lock loop circuit (32) and to a multiplexer (34). The output of the phase lock loop circuit (32) is a second input to the multiplexer (34). The phase lock loop circuit (32) receives its power from a power and control pin (22). The multiplexer (34) receives its power from a power pin (24). The power and control pin (22) is used as a control input to multiplexer (34). Multiplexer (34) uses the power and control pin (22) to select which input to output as a system clock.

Method and apparatus for providing both power and control by way of an

A data processor has an input synchronizer (10) which is dynamically enabled by a plurality of control signals provided by a user of the data processor. When the plurality of control signals has a predetermined logic level, a bias generator enable circuit (18) enables a bias generator (16). Subsequently, bias generator (16) enables a differential amplifier (12) to synchronize an asynchronous input signal to an operating frequency of the data processor. When the plurality of control signals does not have the predetermined logic level, bias generator enable circuit (18) disables bias generator (16). Subsequently, differential amplifier (12) is disabled and the asynchronous input is not synchronized with the internal operating frequency of the data processor. Therefore, because the user may choose the logic levels of each of the plurality of control signals, the user may dynamically disable input synchronizer (10) to minimize the power consumption of the data processor.

Data processing system having a dynamically enabled input synchronizer

A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal indicates that that particular portion of the system is then disabled or otherwise inhibited from interrupting the operation of the data processing portion.

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Austin, TX, United States of America

Donald L Tietjen