Bull Hn Information Systems, Inc.

Donald L Smith

George J Barlow

A multiprocessor system includes a plurality of central subsystem (CSS) units, a plurality of memory units and input/output units which connect in common to a system bus for transferring requests between a pair of units on a priority basis defined by a distributed bus priority network included as part of the system bus. A private bus (P bus) connects all of the CSS units and memory units in common for high speed block data transfers. Each CSS unit includes input circuits which couple to the priority network for detecting when the system bus is in an idle state. P bus logic circuits couple to the P bus and generate a transfer request in response to a request from its CSS unit only when the P bus is detected to be in an idle state. The idle signals from both buses are used to generate a system bus request for P bus access only when both buses are in an idle state so as to eliminate the need to contend for system bus use.

Minimum contention processor and system bus system

A multiprocessor system includes a plurality of identical central subsystem (CSS) units, a plurality of memory subsystem units and input/output units which connect in common to a system bus. Requests are transferred between a pair of units on a priority basis defined by a distributed bus priority network included as part of the system bus. Each CSS unit includes cycle stealer logic circuits which grant bus cycles on a round robin basis. The cycle stealer logic circuits are connected to receive high priority request signals from the network and refuse acceptance of a cycle granted to such CSS unit as a low priority requester thereby passing it along to a next lower priority CSS unit.

Method and apparatus for a high performance round robin distributed bus

A multiprocessor system includes a plurality of identical central subsystem (CSS) units, a plurality of memory and input/output (I/O) subsystem units which connect in common to an asynchronous bus system. Each CSS subsystem unit includes a cancel command mechanism for enabling each such unit to effectively withdraw from the asynchronous bus or switch the state of a resource such as a memory or I/O lock mechanism included in such subsystem without otherwise disturbing the state of such subsystems.

Cancel mechanism for resilient resource management and control

A multiprocessor system includes a system management facility (SMF) unit, a plurality of central subsystem (CSS) units, a plurality of memory subsystem units and first and second pluralities of input/output units which connect in common to a system bus. Requests are transferred between a pair of units on a distributed bus priority network included as part of the system bus on the basis of the unit's physical position on the bus relative to one end of the bus. The SMF unit positioned at the high priority end of the bus includes fast recovery bus request logic circuits which connect to the high priority request line of the priority network. Each of the CSS units positioned after the SMF unit on either side of the memory subsystems includes bus request logic circuits which connect only to the low priority request line. The memory subsystems each include bus request logic circuits which connect to both the high and low priority request lines for accepting and granting cycles from higher and lower priority units. This enables the positioning of the first and second pluralities of input/output units positioned below the memory subsystems to operate as high and low priority requestors.

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Bedford, MA, United States of America

Donald L Smith