Texas Instruments Corporation

Other

Donald L Plumton

Jau-Yuann Yang

Han-Tzong Yuan

Francis J Morris

Tae S Kim

Timothy S Henderson

Yung-Chung Kao

Liem T Tran

Thomas J Aton

Hung-Dah Shih

Antonio L P Rotondaro

Walter Marvin Duncan

Duane E Carter

Shiban Kishan Tiku

Douglas A Prinslow

Stanton Petree Ashburn

Albert H Taddiken

Stephen W Russell

Abha Singh Kasper

Eric D Rullan

Harold C Waite

Daniel Lee Corum

Han-Tzong Yuang

Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.

Methods and devices for determining logical to physical mapping on an integrated circuit

A method for fabricating an integrated circuit includes the steps of: providing a substrate having a semiconductor surface; providing a hardmask material on the semiconductor surface. For at least one masking level of the integrated circuit: providing a mask pattern for the masking level partitioned into a first mask and at least one second mask, the first mask providing features in a first grid pattern and the at least one second mask providing features in a second grid pattern, wherein the first and the second grid pattern have respective features which interleave with one another over at least one area; applying a first photoresist layer with the first mask; exposing the first grid pattern using the first mask; developing the first photoresist layer; etching the hardmask material to transfer the first grid pattern in the surface of the substrate; removing the first photoresist layer.

Integrated circuit having interleaved gridded features, mask set, and method for printing

A method () for fabricating an integrated circuit includes the step of providing a substrate having a semiconductor surface (). For at least one masking level (e.g. gate electrode, contact or via) of the integrated circuit, a mask pattern for the masking level is partitioned into a first mask and at least a second mask (). The first mask provides features in a first grid pattern and the second mask provides features in a second grid pattern. The first and second grid pattern have respective features that interleave with one another over at least one area. A first photoresist film is applied onto the surface of the substrate (). The first grid pattern is printed using the first mask (). The second grid pattern is printed using the second mask (). The first and said second grid pattern are then etched into the surface of the substrate (). Another embodiment of the invention includes an integrated circuit () that has vias or contacts in a grid-like feature pattern in at least one multi-transistor area of the circuit including at least 5 transistors, wherein a minimum horizontal or minimum vertical center-to-center spacing distance between neighboring features in the pattern is &#x2266;100 nm.

Integrated circuit having interleaved gridded features, mask set and method for printing

A dry etch using CFx in an O2-rich environment will clean the contact/via at the same time it retracts a layer of TiN enclosed in the dielectric layer, such as the plate layer in a Capacitor-Under-Bitline DRAM cell.

Simplifying conductive plate/via isolation

A vertical field effect transistor (,) and fabrication method with buried gates (,) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (,) may have modulated doping along the channel (,), and the drain (,) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (,) to form the channels (,).

Epitaxial overgrowth method and devices

A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).

Vertical field effect transistor and diode

A method and structure for a vertical FET transistor device (VFET) is described for a lower junction capacitance VFET to decrease the switching power loss and achieve increased current capacity and/or deceased thermal dissipation. In a preferred embodiment, the gate capacitance is reduced over prior art methods and structures by etching to the gate 14 and directly contacting the p+ gate with a p-ohmic contact 24. In another embodiment, the area under the gate contact 22 is implanted with a 'trim' dopant, where the trim dopant acts to reduce the doping of the drainlayer thereby reducing the capacitance. In another embodiment, the area under the exposed gate contact 22 is isolated by ion damaged to reduce the doping/conductivity of the n- drain layer below a portion of the gate layer to reduce the gate-to-drain capacitance.

Low capacitance power VFET method and device

A voltage regulator (10) comprising a vertical channel transistor (12). The vertical channel transistor (12) may have a gate (16), a voltage input terminal (18), and a voltage output terminal (20). A reference voltage supply (14) may be coupled to the gate (16).

Integrated voltage regulator circuit with vertical transistor

A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (704) may have modulated doping along the channel (706), and the drain (708) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (704) to form the channels (706).

Vertical JFET field effect transistor

A vertical field effect transistor (100) and fabrication method with buried gates; (104) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and connecting structure.

Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs on silicon is accomplished by first growing GaAs (104) on silicon (102), then growing a lattice matched cap of Al.sub.z Ga.sub.1-z,As (106), next annealing out defects with the Al.sub.z Ga.sub.1-z As cap (106) limiting desorption of gallium, lastly growing further GaAs (110) directly on the cap. The lattice matched cap is also used as an implant anneal cap.

Capped anneal

Epitaxial overgrowth method

A self-aligned planar heterojunction bipolar transistor (10) is fabricated by forming a base layer (18) and forming an emitter layer (20) on the base layer (18). An emitter cap layer (22) is formed on the emitter layer (20) and an interface layer (24) is formed on the emitter cap layer (22). A first implantation layer (26) is formed through the interface layer (24), the emitter cap layer (22), and the emitter layer (20) to the base layer (18). A second implantation layer (30) is formed through the interface layer (24), the emitter cap layer (22), and the emitter layer (20) to the base layer (18) and overlaps the first implantation layer (26). A portion of the interface layer (24), the emitter cap layer (22), and the implantation layers (26, 30) are removed and replaced by an insulating region (33). An emitter contact (38) is formed on the remaining emitter cap layer (22) and is isolated from the implantation layers (26, 30) by the insulating region (33). The insulating region (33) acts as a buffer to self-align the emitter contact (38) to the implantation layer (26, 30).

Method of self-aligning an emitter contact in a planar heterojunction

Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs on silicon is accomplished by first growing GaAs (104) on silicon (102), then growing a lattice matched cap of Al.sub.x Ga.sub.1-x As (106), next annealing out defects with the Al.sub.x Ga.sub.1-x As cap (106) limiting desorption of gallium, lastly growing further GaAs (110) directly on the cap. The lattice matched cap is also used as an implant anneal cap.

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Dallas, TX, United States of America

Donald L Plumton