International Business Machines Corporation

Donald L Jordan

Sue Ellen Strang

Steven H Voldman

Dureseti Chidambarrao

Richard Quimby Williams

David S Collins

Tina Jane Wagner

Raminderpal Singh

David M Onsongo

Judith H McCullen

Carl E Dickey

Tina Wagner

System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search 'buckets' that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).

Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models

A computerized method and system for designing, verification and checking of the electrostatic discharge (ESD) protection circuits and their implementation in a integrated computer chip design where the computer chip comprises of electronic circuits designed in a parameterized cell design system, pads, interconnects and the ESD system uses a hierarchical system of parameterized cells (p-cells) which are constructed into higher level ESD networks. Lowest order p-cells pass user defined parameters to higher order p-cells to form an ESD protection circuit meeting design criteria. Ones of the p-cells are 'grow-able' such that they can form repetition groups of the underlying p-cell element to accommodate the design parameters. Layout and circuit schematics are auto-generated with the user varying the number of elements in the circuit by adjusting the input parameters. The circuit topology automation allows for the customer to auto generate new ESD circuits and ESD power clamps without additional design work.

ESD design, verification and checking system and method of use

A method for designing integrated circuits comprising: partitioning interconnects of an integrated circuit design based on partition criteria to create sets of interconnect partitions; selecting at least one analysis method from a set of analysis methods to be performed on interconnects of each set of interconnect partitions; and performing each selected analysis method on interconnects of each corresponding interconnect partition.

Method and system for integrated circuit design

Growing community of inventors

Weybridge, VT, United States of America

Donald L Jordan