Motorola Corporation

Freescale Semiconductor,inc.

Donald L Hughes, Jr

Bertrand Francis Cambou

Bishnu Prasanna Gogoi

Andrew C McNeil

David Joseph Monk

Shiuh-Hui Steven Chen

Carl A Ross

Richard J August

John E Schmiesing

Kevin D Neumann

David W Odle

Andrew C Mcneil

A capacitive pressure sensor ( ) utilizes a diaphragm ( ) that is formed along with forming gates ( ) of active devices on the same semiconductor substrate ( ).

Method of forming an integrated CMOS capacitive pressure sensor

A capacitive pressure sensor and method of fabricating the sensor includes providing a layered structure including a second silicon layer (115), a second insulating layer (203, 205) in contact with the second silicon layer (115), a first silicon layer (123) in contact with the second insulating layer (203, 205), a first insulating layer (201) in contact with the first silicon layer (123), and a mask layer (221) in contact with the first insulating layer (201). A major exposed surface (220) of the second silicon layer (115) is provided by mechanically reducing a thickness (210) of the second silicon layer (115) to a predetermined thickness (116). Preferably this is done by grinding and then polishing the second silicon layer (115). In one embodiment a third insulating layer (211) is in contact with the second major surface (220) of the second silicon layer (115). A third silicon layer (101) having a fourth insulating layer (109) forming a perimeter structure (215) positioned above and surrounding a predefined area (114) of the third silicon layer (101). The perimeter structure (215) is bonded to the third insulating layer (211), wherein a chamber (113) is formed between the third insulating layer (211), the perimeter structure (215), and the predefined area (114). Preferably, a portion of the first silicon layer (123) is removed using an anisotropic etch step.

Capacitive pressure sensor and method of fabricating same

A method is provided for making a power device (54) and a small signal device (52) on a bonded silicon substrate (41). A first silicon substrate (10) provided. A first surface (17) is etched to form a plurality of cavities (11) with a depth (13). A dielectric layer (14) is created on the first surface (17), wherein the dielectric layer (14) is created with a thickness less than or equal to the depth of the plurality of cavities. The dielectric layer (14) is patterned so that a plurality of islands (22) of dielectric remain in the cavities. A second silicon substrate (42) is provided. The first and the second silicon substrates (10, 42) are bonded together in such a manner that the islands (22) are buried. A predetermined portion of the first silicon substrate (10) is removed, thereby creating a surface that is suitable for semiconductor device fabrication.

Vertical and lateral isolation for a semiconductor device

Growing community of inventors

Mesa, AZ, United States of America

Donald L Hughes, Jr