Other

National Semiconductor Corporation

Donald Kevin Cameron

Wai Cheong Chan

A method, apparatus and system for a secure memory with restricted access by processors. System has a plurality of processor units (PUs) coupled to a block of memory with at least one section secured (BMSS) against hacking by not allowing all PUs to access BMSS. One or more PUs has access to BMSS and is implemented with a dedicated function(s) that no other PU can perform such as a security function for encryption key checks. A thread running on a given PU that lacks access to a given memory location in BMSS is transferred to another PU with i) access to given memory location in BMSS; ii) implemented dedicated function; and/or iii) locked down instruction memory not free to run other code. Any attempt to breach protocol issues a fault. Existing code is hardened against less secure user code by only permitting authorized routines to transfer to the implemented PU.

Secure memory with restricted access by processors

In an embodiment, a processing resource allocation method is disclosed. The method may include identifying an instruction mapped to data having a preselected data location. The method may also include determining whether to transfer a call of the instruction from a first processing unit (PU) to a second PU based on the preselected data location.

Improving performance and security of multi-processor systems by moving thread execution between processors based on data location

According to various techniques of the present invention, probability models for circuit simulation are generated as linear, piecewise linear, nonlinear, and/or continuous probability waveforms. These waveforms represent probability values for logic levels over some period of time. Probability models are defined according to characteristics of the electronic components being modeled, so as to capture variability in characteristics and performance of logic circuits and their components. The probability waveforms of the present invention can be used to predict circuit component behavior resulting from state changes; a range in response time can be indicated by a probability waveform indicating the probability that the response has taken place at a given time after an input state change. Construction of a probability model for a circuit with interconnected electronic components allows timing problems resulting from variability in component performance to be identified.

Including variability in simulation of logic circuits

A system and method for slack determination in a logic integrated circuit. A launch pulse is input to a circular delay loop circuit. The leading edge of the launch pulse causes a pulse to circulate around the circular delay loop. The number of passes made through the loop by the circulating pulse is counted by a latch/counter circuit. A sample pulse is input to the latch/counter circuit to latch the number of pulse circulations at the leading edge of the sample pulse. The pulse circulation count provides delay information in the circuit that may subsequently be used to adjust a supply voltage in the integrated circuit.

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Sunnyvale, CA, United States of America

Donald Kevin Cameron