Intel Corporation

Donald K Newell

Ravishankar Iyer

Li Zhao

Ramesh Kumar Illikkal

Srihari Makineni

Andrew J Herdrich

Vineet Chadha

Sujoy Sen

Rameshkumar G Illikkal

Dave B Minturn

Ravi Iyer

Jianping Zhou

Zhen Fang

Jaideep Moses

Rajiv Choudhary

David W Doerner

Ramesh G Illikkal

Yong Zhang

Simon C Steely, Jr

Martin Guy Dixon

Hari Kannan

Quinn Able Jacobson

Mingqiu Sun

William C Hasenplaugh

Antonio Gonzalez

Fernando Latorre

David M Putzolu

Aamer Jaleel

David B Minturn

Leena K Puthiyedath

Pedro Lopez

Jaume Abella

Suresh Srinivas

Josep M Codina

Tong Li

Sadagopan Srinivasan

Erik Hallnor

Liqun Cheng

Jose-Alejandro Pineiro

Enric Gibert

Jeffrey S Wilder

Carl Lebsack

Ramesh Milekal

Srihari Makikeni

Ravishankar Iver

In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

Packet coalescing

An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

Methods and apparatuses for controlling thread contention

Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.

Optimized fast hessian matrix computation architecture

A system for controlling use of broadcast content is described. In accordance with a particular implementation, the system includes a receiver in communication with a source of broadcast content. The receiver also includes, or is coupled to, a playback device. The receiver is configured to control the use of received broadcast content through the playback device in accordance with control information embedded in the broadcast content.

System for controlling use of broadcast content

In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory may filter an access to one or more ways of a selected set of the cache memory based at least in part on a current privilege level of a processor and the ring level identifier of the one or more ways. Other embodiments are described and claimed.

Controlling access to a cache memory using privilege level information

Growing community of inventors

Portland, OR, United States of America

Donald K Newell