Ncr Corporation

Other

Donald K Lauffer

Ikuo J Sanwo

Warren W Porter

William P Ward

Paul M Rostek

Donald G Tipon

Gregory Howard Milby

Mehdi H Sani

Martha A Lauffer

A method and apparatus for introducing gradual changes to an audio signal so that the changes are subliminal. The changes can involve tempo and volume, for example, and can take the form of a gentle gradient having ever increasing/decreasing ramp-like changes over a sufficient duration, or a more complex program involving several gentle gradients. In the preferred embodiment, an enhanced audio play-back device such as a portable audio cassette recorder can be programmed to subliminally alter the characteristics of a standard pre-recorded tape containing music, for example. As a motivational tool during walking, jogging or other repetitive exercise, the tempo is gradually increased over a period of time to encourage a corresponding gradual (and subliminal) increase in physical exertion by a user whose rate of movement is proportional to the tempo of the music. The tempo can be either manually changed in conjunction with a subliminal program, or by itself in an override mode, or by itself in a version of the present-inventive audio play-back device which allows only manual tempo alternation. In an alternate embodiment, a special pre-recorded tape contains subliminal changes in tempo, for example, for play-back on a standard audio cassette recorder (which operates at one speed, only) to cause the same effect as the preferred embodiment.

Method and apparatus for introducing subliminal changes to audio stimuli

A CMOS circuit having an input threshold, the CMOS circuit including a first field-effect transistor having a source connected to a first power supply terminal, a drain connected to an output terminal, a gate connected to an input terminal, and a first channel between the source and the drain having a first width and a first length. A programmable field-effect transistor circuit has a gate terminal connected to the input terminal, a drain terminal connected to the output terminal, a source terminal connected to a second power supply terminal, and a second channel circuit between the drain terminal and the source terminal having an effective width and an effective length. Programmable input terminals are connected to the second channel circuit for changing the ratio of the product of the first width times the effective length to the product of the effective width times the first length such that the input threshold voltage of the CMOS circuit is changed responsive to the change of the ratio. By programming the input terminals and selecting the voltages on the first and second power supply terminals, a universal input buffer for conversion of one logic level voltage to another may be provided.

CMOS circuit with programmable input threshold

A cryogenically cooled integrated circuit apparatus is disclosed. The apparatus includes a cryogenic vessel with an integrated circuit package positioned in an opening at one end. One face of the integrated circuit is in direct contact with cryogenic fluid and a second face has a standard pin array which is connectable to a printed circuit board.

Cryogenically cooled integrated circuit apparatus

Methods and apparatus for lowering integrated circuit (IC) chip ambient temperatures allow a slow IC chip to simulate a faster, functionally equivalent one for design testing purposes when the faster chip is not yet available. The cooling devices employed include a cryogenic chip cooling apparatus, and a novel thermo-electric chip cooling apparatus using a directly water-cooled Peltier effect device attached to the surface of the IC chip.

Method and apparatus for low temperature integrated circuit chip testing

A pin grid array package for carrying an integrated circuit chip having input/output leads. The pin grid array package includes a carrier having a centrally located opening for carrying the integrated circuit chip, a plurality of input/output pins spaced around the periphery of the centrally located opening, interconnect leads on the carrier for connecting selected ones of the input/output pins to selected leads of the integrated circuit chip, and heat sink material around the periphery of the input/output pins which serves as a cooling-fin for efficient integrated circuit chip heat removal. Each of the plurality of input/output pins is normal to the plane of the integrated circuit chip and extends through the carrier with a first portion extending away from a first side of the carrier and a second portion extending away from a second side of the carrier. The first portion of each input/output pin has a centrally located passage therein, and the second portion has a reduced pin portion for pluggable engagement with a centrally located passage of a similar input/output pin such that the pin grip array package is stackable.

Stackable integrated circuit chip package with improved heat removal

A printed circuit board assembly is disclosed which includes a number of rigid printed circuit boards connected by a number of flexible printed circuit panels. Integrated circuits and similar components are mounted on the rigid printed circuit boards. The components are interconnected by printed circuit conductors of the rigid printed circuit boards and the flexible printed circuit panels. The resulting board assembly can provide a manifold increase in the usable component area over a single flat, rigid printed circuit board when it is folded and installed into a standard cylindrical, coolant filled container.

Foldable printed circuit board

A cryogenic vessel for cooling electronic components, wherein the cryogenic vessel includes a pair of vessel portions, each vessel portion having an outer wall and an interior immersion chamber. A membrane member is located between the vessel portions for separating the mentioned immersion chambers. The membrane member includes openings for providing fluid transfer between the immersion chambers of the vessel portions and a portion extending from between the vessel portions to a point exterior of the vessel portions. Sealing members are located between the membrane member and each of the vessel portions for providing a fluid tight seal of the immersion chambers. An electronic component mounting socket is located on a portion of the membrane member within the immersion chambers for mounting an electronic component to be cooled. A supply conduit through the outer wall of one of the vessel portions introduces cryogenic fluid into the immersion chambers.

Cryogenic vessel for cooling electronic components

Apparatus and method for removably mounting an integrated circuit package having a plurality of electrical pins wherein a plurality of mating pins each having a receptacle filled with liquid mercury are connected to the electrical pins of the integrated circuit package and the temperature reduced such that the liquid mercury solidifies thereby firmly bonding the electrical pins together. The assembly may be inserted into a Dewar type vessel and covered with a low temperature liquified gas for the dual purpose of solidfying the liquid mercury and cooling the integrated circuit package.

Cryogenic packaging scheme

A terminator for a transceiver device for transmitting data signals to and receiving data signals from a second transceiver device over a transmission line therebetween. The terminator has a transmitter connected to the transmission line for transmitting data signals to the second transceiver device, a receiver connected to the transmission line for receiving data signals from the second transceiver device, a termination resistor connected to the transmission line for improving the transmission characteristics of the transmission line, and a switch device between the termination resistor and the transmission line. The switch device is closed for a portion of the time when the receiver is receiving data signals from the second transceiver device such that when it is closed the termination resistor is connected to the transmission line, and is open for the remainder to the time such that when it is open the termination resistor is not connected to the transmission line.

Terminator for a cmos transceiver device

The circuit of the present invention converts CMOS logic level signals to corresponding ECL logic level signals to permit the coupling of CMOS and ECL devices. In addition, the present invention maintains a relatively constant impedance as the logic levels on its output change. The circuit has an input terminal connectable to a source of a first set of logic signals and an output terminal connectable to a device that is responsive to a second set of logic level signals. First and second power terminals are provided for connection to first and second power supplies, respectively. A transistor of first conductivity type having first, second and gate terminals is provided with the gate terminal connected to the input terminal and the first terminal connected to the first power supply terminal. A second transistor of opposite conductivity type having a first, second and gate terminal is provided with the gate terminal of the second transistor connected to the second terminal of the first transistor. The second terminal of the second transistor is connected to the output terminal and the first terminal of the second transistor is connected to the second power supply terminal. A saturation means is connected between the gate terminal and the second terminal of the second transistor. The saturation means is responsive to the signal on the input terminal for saturating the second transistor in an 'ON' state when the logic level 0 is applied to the input terminal.

CMOS to ECL converter-buffer

The present invention is a temperature compensating circuit adapted for use with a CMOS to ECL interfacing circuit which uses one normally unused ECL logic gate, formed on a chip of many ECL logic gates for generating the supply voltages for the level interfacing circuit such that the output voltage levels from the interfacing circuit will automatically track with the temperature experienced by the chips' ECL logic gates.

Temperature compensated CMOS to ECL translator

A circuit for assisting transitions of a signal on a bus conductor having a sensing element connected to the bus conductor for determining if the bus conductor is in a first state or a second state, an assisting element for assisting transitions of a signal on the bus conductor between its first state and its second state responsive to electrical clock pulses, and a logic element connected to the sensing element and the assist element for enabling said assist element when the transmission of the mentioned signal is from its first state to its second state during said clock pulses, and for disabling the assisting element when the mentioned signal transition is from its second state to its first state during said clock pulses.

Assist circuit for a data bus in a data processing system

A coding technique and circuit implementation for reducing the number of electrical contacts to a memory device, which memory device is configured as part of a monolithic structure. Memory selection is achieved by changing at least one characteristic of a clock signal, such as pulse width. A read or write operation is selected by a mode selector, the level of which is determined by the level of the signal on a function contact when memory selection is achieved.

Minimum pin memory device

A circuit for reducing the number of external pins or terminals on a memory device includes a counter circuit which periodically causes the signal on a first external pin to be provided to the power terminal of an internal power supply within the memory device and, at the same time, causes the ground level signal on a second external pin to be provided to the ground terminal of the internal power supply. At other times during the receipt of signals on the two external pins, the signal on the first pin provides both memory select and clocking functions and the signal on the second pin provides memory mode select, address, and data input and output functions.

Memory device having a minimum number of pins

A memory device includes a circuit for reducing the number of pins or external terminals on the memory device. A threshold detector within the circuit detects the difference in voltage between signals applied at two external pins. A clocking signal at one pin provides, in addition to a synchronizing function, a memory device select function, and a signal at the other pin provides memory mode select as well as memory address, data input and data output functions. Switching transistors controlled by the output of the threshold detector connect the external pins to the power and ground terminals of an internal power supply so that the signals at the two external pins also provide the power and ground signals to the memory device.

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Poway, CA, United States of America

Donald K Lauffer