Synopsys, Inc.

Donald John Oriordan

Jonathan Lee Sanders

Friedrich Gunter Kurt Sendig

Salem Lee Ganzhorn

Barry Andrew Giffel

Hsiang-Wen Jimmy Lin

Jingyu Xu

Guy Morency

Bulent Basaran

Larissa Nitchougovskaia

Yevgenia Murad Beglaryan

Nabil Yazdani

Liana Badalyan

Gajanan Madhukarrao Joshi

Ruben Grigoryan

Hui Xu

A method, a system, and non-transitory computer readable medium for aging analysis are provided. The method includes performing stress simulations for a plurality of process, voltage, temperature (PVT) conditions for a circuit, the circuit including one or more devices, extrapolating device level stresses obtained from the stress simulations into device level parameter degradations to a desired circuit age; and performing degradation simulations for the circuit for the same PVT conditions based on the device level parameter degradations. Each degradation simulation for a PVT condition of the plurality of PVT conditions is performed using the device level parameter degradations associated with the same PVT condition.

Full correlation aging analysis over combined process voltage temperature variation

The independent claims of this patent signify a concise description of embodiments. Roughly described, disclosed is technology for yield improvement of an integrated circuit device implementing a circuit design which includes, in a first verification, verifying adherence of the circuit design to a set of performance specifications, over a first set of test cases which include variations in a fabrication process variable or an environmental condition. The verification includes identifying, for each test case of the first set of test cases, an extent to which the circuit design satisfies one or more of the performance specifications of the set of performance specifications. A second circuit design is then developed to address corner cases identified in the first verification, and the second circuit design is then re-verified using only a subset of test cases having test cases fewer than test cases of the first set of test cases.

Extreme cases sampling method for improved variation-aware full custom design

The independent claims of this patent signify a concise description of embodiments. Embodiments described herein are directed to a database-driven scheme for automating the process of VDRC checking in a full-custom EDA Design and Implementation tool. Various embodiments include at least a computer-implemented method of performing Voltage-based Design Rule Checking (VDRC) in a full-custom EDA Design and Implementation Platform is provided, the method comprising receiving a plurality of net voltages from at least a first net and a second net, wherein reception of the plurality of net voltages is from one or more of a simulation, a plurality of simulations, manual override, or direct input, determining a net voltage range, the net voltage range being a difference between a first net voltage of a first net and a second net voltage of a second net, causing transfer of the net voltage range to a layout editing process, the layout editing process resulting in generating a layout, and performing VDRC verification, confirming a VDRC clean layout. This Abstract is not intended to limit the scope of the claims.

Full-custom voltage-dependent design rules (VDRC) flow

Systems and method for generating graphical visualizations of an integrated circuit (IC) design may comprise configurations for generating interactive graphical visualizations of the IC design configured for providing informative overlays to the graphical visualizations based on a selected zoom level of the graphical visualization. In certain embodiments, the graphical overlays may be generated over corresponding objects for providing information regarding hierarchies of objects, or for generating perceptible overlays over objects regardless of a zoom level of the interactive graphical visualization.

Hierarchical dynamic heat maps in full custom EDA applications

A method for reuse of extracted layout-dependent effects for circuit design using circuit stencils includes receiving a schematic of an integrated circuit including a circuit segment. A circuit stencil corresponding to the circuit segment is instantiated in a schematic of a second integrated circuit. The circuit stencil includes layout-dependent effects information for the circuit segment extracted from a layout of the first integrated circuit. Simulation is performed on the schematic of the second integrated circuit using the layout-dependent effects information for the circuit segment. A layout of at least a portion of the second integrated circuit corresponding to the circuit segment is generated responsive to performing the simulation.

Reuse of extracted layout-dependent effects for circuit design using circuit stencils

Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.

Integrated circuit design using generation and instantiation of circuit stencils

A bi-directional EDA-browser bridge mechanism enables an EDA system and its related (external) tools to interact with a browser. The EDA-browser bridge uses a design markup language (DML) to communicate with the browser, using a document-based approach rather than a more traditional programming/API-based approach to extending (e.g., integrating tools) the EDA system. By using a markup language, extending the EDA system becomes more accessible to a wider community of developers (e.g., those with web development skills, as opposed to those with just EDA programming skills), and be able to leverage a wider variety of powerful third-party libraries, such as jQuery or D3. For example, developers are able to more easily generate interactive interfaces for viewing results related to the EDA system.

Scheme and design markup language for interoperability of electronic design application tool and browser

A selection of a source testbench is received from a user. The source testbench includes a description of one or more source parameters, a description of one or more source measurements, and a plurality of source entries, each of the source entries including a value for each of the one or more source parameters and each of the one or more source measurements. Furthermore, a selection of a destination testbench is received. The destination testbench includes a description of one or more destination parameters and a plurality of destination entries including a value for each of the one or more destination parameters. One or more source entries are matched with a destination entry. One or more source measurements of the matched one or more source entries are aggregated based on an aggregation function, and the aggregated source measurements are mapped to the matched source entry.

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Sunnyvale, CA, United States of America

Donald John Oriordan