Ramtron International Corporation

Hitachi, Ltd.

Cypress Semiconductor Corporation

Donald J Verhaeghe

Yoshihiko Yasu

Hiroyuki Sakai

Shan Sun

William F Kraus

Thomas Davenport

Michael W Yeager

Steven D Traynor

Robert Sommervold

Dennis R Wilson

Alan D DeVilbiss

Fan Chu

Jayant Ashokkumar

Judith E Allen

Gregory M Smith

Qidao Li

A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM) circuit, in which the F-RAM circuit stores a bit of data from the SRAM circuit during power-out periods, the F-RAM circuit is further coupled to bit-line(s) to output the bit of data stored in the F-RAM circuit when operation power is restored.

Non-volatile static RAM and method of operation thereof

A method of minimizing imprint in a ferroelectric capacitor uses a gradually attenuated AC field to electrically depolarize the ferroelectric capacitor before being packaged. The AC field is linearly attenuated, and generated using a series of voltage pulses, down to a minimum allowed voltage. A final pulse is a positive voltage to minimize hydrogen degradation during packaging. Thermal depoling can also be used.

Method minimizing imprint through packaging of F-RAM

A method for improving data retention in a 2T/2C ferroelectric memory includes baking a ferroelectric memory configured to operate as an array of 1T/1C memory cells for a period of time, and then configuring the ferroelectric memory to function as an array of 2T/2C memory cells, wherein the baking pre-imprints the ferroelectric capacitors in the ferroelectric memory and stabilizes a 2T/2C opposite state margin and enhances data retention. A corresponding memory circuit for configuring an array of memory cells for either 1T/1C operation or 2T/2C operation includes a plurality of sense amplifiers, a configurable reference circuit coupled to a logic circuit, a memory array, and a column decoder, wherein components are coupled together through a bit line and a complementary bit line, and wherein the logic circuit can configure the reference circuit for 1T/1C operation or 2T/2C operation.

Method for improving data retention in a 2T/2C ferroelectric memory

A bootstrap circuit suitable for use in driving the word line of a FRAM.RTM. memory circuit is energized by a VDD power supply voltage. The bootstrap circuit includes a first N-channel MOS transistor wherein the source/drain forms the input of the circuit. A second N-channel MOS transistor is included wherein one of the source/drains receives a clock signal, and the other source/drain forms the output, which drives the word line. The gate of the second transistor is coupled to the other source/drain of the first transistor. The bootstrap circuit includes further circuitry for generating a voltage greater tan the VDD power supply voltage that is coupled to the gate of the first transistor. A capacitor or capacitor-connected transistor is coupled between the input and the gate of the first transistor, and a third transistor has one source/drain coupled to the gate of the first transistor, and the other source/drain receives a control signal, and the gate is coupled to the VDD power supply. The bootstrap circuit is operational even for VDD power supply voltages less than or equal to 3.3 volts.

Low voltage bootstrapping circuit

A method of driving a selected plate line segment in a 1T/1C memory, the method including the steps of logically combining an odd word line signal and an even word line signal to form a first logic signal, logically combining the first logic signal with a plate clock signal to form a second logic signal, latching the second logic signal, and driving the selected plate line segment with the latched second logic signal.

Plate line driver circuit for a 1T/1C ferroelectric memory

A semiconductor memory device, divided into plural blocks, comprising: a memory array having a non-volatile memory element which makes the read cycle and the write cycle to be substantially equivalent; plural storage elements storing the information of write protection/permission corresponding to each said block respectively; and a setting circuit to set the information of write protection/permission to said plural storage elements, wherein said setting circuit sets the write-protection information to said plural storage elements at the write cycle after designated plural read cycles. Therefore, the write protection/permission can be set by the unit of block, block by block, so that the write-protected ROM and the RAM can be set freely. Furthermore, the complexity of the setting procedure of write protection/permission may prevent the accidental false setting caused by a system runaway and so forth.

Write Protection for a non-volatile memory

A semiconductor memory device, divided into plural blocks, includes a memory array having a non-volatile memory element in which address access times for the read cycle and the write cycle are substantially equivalent to one another (for example, a ferroelectric memory element). Plural storage elements stores the information for write protection/permission corresponding to each of the blocks, respectively. A setting circuit is provided to set the information for write protection/permission to the plural storage elements. The setting circuit sets the write-protection information to the plural storage elements at the write cycle after designated plural read cycles. Therefore, the write protection/permission can be set in block units block by block, so that the write-protected areas for a ROM and a RAM formed by the non-volatile memory element can be set freely. Furthermore, the complexity of the setting procedure for write protection/permission serves to prevent accidental false setting caused by system runaway or the like.

Semiconductor memory device

A circuit and method for reducing compensation of a ferroelectric capacitor in a cell of a memory array allows the capacitor's hysteresis loop to be repositioned toward its uncompensated position by pulsing the electrodes of the memory cell capacitors, via the memory array plate line, one or more additional times whenever a 'write' occurs to the memory array. As a result, the ferroelectric capacitor delivers a signal of greater strength to the memory device sense amps upon a subsequent 'read' operation significantly enhancing overall reliability and yield yet without reducing overall device endurance.

Circuit and method for reducing compensation of a ferroelectric

A test mode circuit for an integrated circuit includes a high voltage detector having an input for receiving a high voltage signal, a Schmitt trigger having an input coupled to the output of the high voltage detector, a latch having an input coupled to the output of the Schmitt trigger and an output for providing a test mode signal in a test operational mode, and additional control circuitry for disabling the high voltage detector and Schmitt trigger so that substantially all of the active current flow in the high voltage detector and Schmitt trigger is eliminated in a normal operational mode. The test mode circuit further includes circuitry for preventing a reset condition in the latch during the test mode until a power-down condition occurs. A glitch filter is also included, which is interposed between the output of the Schmitt trigger and the input to the latch. An integrated circuit pin is coupled to both the test mode circuit and to other circuitry on the integrated circuit not forming part of the test mode circuit.

Low-power non-resetable test mode circuit

Circuit and method for reducing a compensation of a ferroelectric

A filter circuit includes an input node for receiving an unfiltered input signal, an output node for providing a filtered output signal, and an intermediate node. An integrator has an input coupled to the input node and an output coupled to the intermediate node. A Schmitt trigger has an input coupled to the intermediate node and an output coupled to the output node. A reset circuit has a first input coupled to the input node, a second input coupled to the output node, and an output coupled to the intermediate node. The signal on the intermediate node is generated by integrating the unfiltered logic input signal if the input signal and the output signal are at opposite logic states. A filtered output logic signal is generated by conditioning the intermediate signal with the Schmitt trigger. The reset circuit resets the intermediate signal if the input signal and the output signal are each at a zero logic state or if the input signal and the output signal are each at a one logic state.

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Colorado Springs, CO, United States of America

Donald J Verhaeghe