Rca Inc.

David Sarnoff Research Center, Inc.

Sarnoff Corporation

Rca Thomson Licensing Corp.

Nippon Sheet Glass Company, Limited

Rca Licensing Corporation

General Electric Company

Harris Corporation

Imation Corporation

Digital Imaging Systems Gmbh

Donald J Sauer

Peter Alan Levine

Nathaniel Joseph McCaffrey

Robert Amantea

Ramon Ubaldo Martinelli

William E Rodda

Edward R Campbell, Iii

Walter F Kosonocky

Danny Chin

Dalton H Pritchard

Kazuo Katsuki

Todd J Christopher

Lubomir L Jastrzebski

Nang T Tran

Francis Dell'Ova

Dietrich Meyerhofer

Francis Paul Pantuso

Ronald J Johansson

Neil J McCaffrey

Frank P Pantuso, Sr

A new multiple imager array device is achieved. The device comprises, first, a bi-directional bus. An array of imagers is arranged in n rows and m columns. The n and m are positive integers. Each imager is connected to the bi-directional bus. A line of bits of any imager is accessible by a line address. Each imager has a Vmode input and an output enable input. The Vmode input and the output enable input must be enabled to allow accessing. A first multiplexer has an input and a plurality of outputs. The input is connected to a column counter. Each output is connected to the output enable input of one of the imagers. A second-multiplexer has an input and a plurality of outputs. The input is connected to a row counter. Each output is connected to the Vmode input of each imager in one of the rows.

Multiplexing prism CMOS imagers to a single data bus

In one embodiment, an imager has an array of photodetectors, each of which accumulates charge during an integration period as a result of light detected during the integration period, the array having a charge capacity which increases during the integration period. A charge capacity controller coupled to the imager adjusts how the imager increases the charge capacity of the array based upon the brightness distribution detected by the imager during at least one previous integration period.

Extended dynamic range imaging system and method

An infrared imager includes an array of capacitance sensors that operate at room temperature. Each infrared capacitance sensor includes a deflectable first plate which expands due to absorbed thermal radiation relative to a non-deflectable second plate. In one embodiment each infrared capacitance sensor is composed of a bi-material strip which changes the position of one plate of a sensing capacitor in response to temperature changes due to absorbed incident thermal radiation. The bi-material strip is composed of two materials with a large difference in thermal expansion coefficients and an amorphans silicon a corbide layer.

Infrared imager using room temperature capacitance sensor

An extended dynamic range imager. An array of pixels provides an output signal for each pixel related to an amount of light captured for each pixel during an integration period. A row of extended dynamic range (XDR) sample and hold circuits having an XDR sample and hold circuit for each column of the array captures an XDR signal related to a difference between the output signal and an XDR clamp level to which the pixel is reset at a predetermined time before the end of the integration period. A row of linear sample and hold circuits having a linear sample and hold circuit for each column of the array captures a linear signal related to a difference between the output signal and an initial output signal to which the pixel is reset at the beginning of the integration period.

Extended dynamic range image sensor system

A correlated double-sampling circuit for sampling an input signal received from a pixel sensor circuit via an input line. According to one embodiment, a first switch selectively couples a junction of first terminals of a first capacitor and a second capacitor to the input line. A second switch selectively couples an output node coupled to a second terminal of the second capacitor to a reference voltage. A third switch selectively couples the output node to an output line.

CMOS image sensor with reduced fixed pattern noise

An infrared imager includes an array of capacitance sensors that operate at room temperature. Each infrared capacitance sensor includes a deflectable first plate which expands due to absorbed thermal radiation relative to a non-deflectable second plate. In one embodiment each infrared capacitance sensor is composed of a bi-material strip which changes the position of one plate of a sensing capacitor in response to temperature changes due to absorbed incident thermal radiation. The bi-material strip is composed of two materials with a large difference in thermal expansion coefficients.

A imager has an array of photodetectors, each of which accumulates charge during an integration period as a result of light detected during said integration period, said array having a charge capacity which increases during the integration period. A charge capacity controller coupled to said imager adjusts how the imager increases the charge capacity of the array based upon the brightness distribution detected by said imager during at least one previous integration period.

Extended dynamic imaging system and method

The invention relates to an extended dynamic range imager. An array of pixels provides an output signal for each pixel related to an amount of light captured for each pixel during an integration period. A row of extended dynamic range (XDR) sample and hold circuits having an XDR sample and hold circuit for each column of the array captures an XDR signal related to a difference between the output signal and an XDR clamp level to which the pixel is reset at a predetermined time before the end of the integration period. A row of linear sample and hold circuits having a linear sample and hold circuit for each column of the array captures a linear signal related to a difference between the output signal and an initial output signal to which the pixel is reset at the beginning of the integration period.

Pixel array including a high resolution mode and a low resolution mode and method of reading out the pixel array in a high and low resolution mode. The pixel array includes a first signal line and a second signal line. An array of pixel elements are provided, each pixel element coupled to the first signal line or the second signal line. A switch mechanism is provided for coupling the first signal line to the second signal line. A mechanism is also provided for conveying a charge associated with each pixel element to the first signal line or the second signal line. A mechanism may also be provided for buffering signals between the first signal line, the second signal line, and an output signal line.

Pixel array with high and low resolution mode

An imaging system and method for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager of the imaging system. According to one embodiment, a plurality of gain correction coefficients having an initial value and a plurality of dc offset correction coefficients having an initial value are stored. A reference dc offset value and a reference gain value are determined, and a dc offset value and a gain value for each CDS circuit is determined. The dc offset value and gain value for each CDS circuit is compared to the reference dc offset value and reference gain value, respectively, and the plurality of gain correction coefficients and the plurality of dc offset correction coefficients is updated in accordance with the comparisons.

DC offset and gain correction for CMOS image sensor

An active pixel sensor circuit and method. According to one embodiment, a photodetector produces a voltage at a floating diffusion node in accordance with light sensed by the photodetector. An active element is coupled at a control terminal to the floating diffusion node and is directly couplable at an output terminal to an output line. The active element is configured to provide an output voltage on the output line having a magnitude related to the magnitude of the floating diffusion node voltage.

CMOS image sensor with improved fill factor

The invention relates to an apparatus and method for detecting electrical charge with a long integration time and in particular to a sampling method which reduces noise that affects the accuracy of the measurement of the total charge. The apparatus samples the charge on the capacitor at the start of the integration period to obtain a sample proportional to a first noise component. It then samples the charge on the capacitor at the end of an integration period and subtracts the noise component sample from the integrated charge sample to obtain a measure of integrated charge to the relative exclusion of the noise component. The circuit uses a folded cascode amplifier and at least one correlated double sampling circuit. The charge detector can be used with any apparatus which generates electrical charge in response to an input including for example, a photodetector, photomultiplier, ion detector, e beam detector and piezoelectric charge detector and arrays of such devices.

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Allentown, NJ, United States of America

Donald J Sauer