International Rectifier Corporation

Infineon Technologies Americas Corp.

Fairchild Semiconductor Corporation

National Semiconductor Corporation

Donald J Desbiens

Robert T Carroll

Gary D Polhemus

Paul J Howell

John W Eldridge

According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.

Electrical connectivity for circuit applications

According to example configurations herein, a leadframe includes a connection interface. The connection interface can be configured for attaching an electrical circuit to the leadframe. The leadframe also can include a conductive path. The conductive path in the leadframe provides an electrical connection between a first electrical node of the electrical circuit and a second electrical node of the electrical circuit. Prior to making the connection between the electrical circuit and the leadframe, the first electrical node and the second electrical node can be electrically isolated from each other. Subsequent to making connection of the electrical circuit with the leadframe, the conductive path of the leadframe electrically connects the first electrical node and the second electrical node together. Accordingly, the leadframe provides connectivity between nodes of an electrical circuit in lieu of having to provide such connectivity at, for example, a metal interconnect layer of an integrated circuit device.

A power system with a fuel cell array is integrated with power, conversion and control circuitry forming an assembly on a single chip. The power system may include mounted discrete components or flip chips. The power transistors may be built with contacts on both top and bottom of the chip, where the large area on the bottom allows for high power dissipation and current densities. Electrical connections are made between the components by etched runs or integrated layers, as is typically found in integrated circuits. The control functions include controlling the gas flowing in the fuel cell channels in response to the power supplied. Temperature and pressure may be measured and used to optimize the power system operation.

Integrated fuel cell power conditioning with added functional control

A contact test structure and method provide accelerated testing of long term reliability of metal to silicon ohmic contacts and adjacent PN junctions on IC dies of a wafer. At least one wafer level reliability contact test structure (10) is formed on the wafer during CMOS or BICMOS wafer fabrication mask sequences without additional steps. A shallow layer (N+S/D) of semiconductor silicon material of second type carrier (N) conductivity is formed in a well (PWELL) of first type carrier (P) conductivity silicon material with a shallow PN junction (J) between the shallow layer and well. Metal to silicon first and second test contacts (TC1,TC2) of metal layer portions (M1) are formed at first and second locations on the shallow layer (N+S/D) spaced apart a selected distance. The second test contact (TC2) has a contact area between a metal layer (M1) and shallow layer (N+S/D) in the minimum size range for the fabrication process for maximizing current density through the second test contact (TC2). The first test contact (TC1) has a substantially greater contact area. A large current is forced in a conductive path through the shallow layer (N+S/D) between the first and second test contacts (TC1,TC2). Changes in the resistance of the conductive path caused by changes in the contact resistance of the second test contact TC2 over time are monitored as a function of applied first and second voltages (V1,V2) and forced current. Additional contact test structure is formed on the well with an ohmic contact layer (P+S/D) spaced from the shallow layer (N+S/D) and metal to silicon third test contact (TC3) to detect occurrence of junction spiking.

Wafer level reliability contact test structure and method

An improved process for fabricating modified isoplanar integrated circuits with enhanced density incorporates a number of interactive and co-acting process steps. First, oxide isolation of epitaxial islands is effected in a two step process, forming a thin thermally grown oxide layer (32), over the surfaces of shallow trenches and then filling the shallow trenches with deposited low temperature oxide (34). Second, an enhanced single polycrystalline or polysilicon layer process uses a blanket implant, eliminates certain masking and etching steps, and defines the polycrystalline layer. Third, a new method and structure is provided for dielectrically isolating and separating contact locations on different surface levels of the integrated circuit structure adjacent to step locations between the surface levels. Finally, a new method constitutes all of the electrical contact locations for the elements of the integrated circuit structure at the same substantially isoplanar level.

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Yarmouth, ME, United States of America

Donald J Desbiens