Xilinx, Inc.

Tsi Telsys, Inc.

Other

Donald J Davis

Jonathan C Harris

Ian D Miller

Toby D Bennett

Stephen G Edwards

Andreas Benno Kollegger

James E Jensen

Christopher R S Schanck

James W Bishop

Yung-Sheng Yu

Christopher Robert Sunderland Schanck

A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model () and identifying data input to each component specified in the language independent model to determine a latency for each component (). The components of the language independent model can be annotated for generation of control signals such that each component is activated when both control and valid data arrive at the component (). Each component also can be annotated with an output latency derived from a latency of a control signal for the component and a latency determined from execution of the component itself ().

Scheduling hardware generated by high level language compilation to preserve functionality of source code design implementations

A method of processing a program written in a general purpose programming language to determine a hardware representation of the program can include generating a language independent model of the program written in a general purpose programming language () and identifying a loop construct within the language independent model (). A determination can be made as to whether the loop construct is bounded (). If so, a loop processing technique can be selected for unrolling the loop construct according to stored user preferences). The loop construct can be replicated in the language independent model as specified by the selected loop processing technique ().

Determining hardware generated by high level language compilation through loop optimizations

The compilation of a high-level software-based description of an algorithm into efficient digital hardware implementation(s) is addressed. This is done through the definition of new semantics for software constructs with respect to hardware implementations. This approach allows a designer to work at a high level of abstraction, while the semantic model can be used to infer the resulting hardware implementation. These semantics are interpreted through the use of a compilation tool that analyzes the software description to generate a control and data flow graph. This graph is then the intermediate format used for optimizations, transformations and annotations. The resulting graph is then translated to either a register transfer level or a netlist-level description of the hardware implementation.

Means and method for compiling high level software languages into algorithmically equivalent hardware representations

A system and method for sending and receiving data with a reliable communication protocol. The system includes a computer at a node having a backplane, a CPU board plugged into the backplane, software instructions for the CPU, and a special network board plugged into the backplane. The CPU board, software, and network card act to implement the TCP/IP protocol suite. The network card or board includes an interface to receive data packets from the physical layer, and circuitry to verify the TCP checksum before de-encapsulation and routing of the TCP segment by the network layer software. It also includes circuitry to automatically prepare the acknowledgement signal to be sent by the receiving computer to the sending computer. It additionally includes circuitry to calculate the error detecting code on outgoing signals from the sending computer to the receiving computer.

System for transmitting and receiving data within a reliable communications protocol by concurrently processing portions of the protocol suite

A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further controlling and executing the hardware objects via high level software constructs and managing the reconfigurable resources, such that the reconfigurable resources are optimized for the tasks currently executing.

System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects

Apparatus and method for constructing data for transmission within a

A programmable circuit assembly and methods for high bandwidth data processing. The assembly includes an array of in-circuit programmable logic packages interconnected with an array of memory packages, allowing for elastic buffering of data in a variety of directions. Each programmable package includes package leads, a memory, and output drivers. Each output driver is connected to a respective package lead, which is configured to generate a logic function defined by programming data stored in the memory. A method includes storing programming data for operating the assembly to send signals on different paths between a programmable package and a memory package.

Programmable circuit assembly and methods for high bandwidth data

A lighted cassette holder for displaying and protecting cassettes is disclosed. The cassette holder features a plurality of cassette holding tracks which are diagonally convergent. The tracks are held by a support member which is attached to a base and a top plate. Electrical lighting is provided adjacent the top plate. Movable dust shields are mounted between the base and top plate to protect the cassettes from dust accumulation.

Growing community of inventors

Ellicott City, MD, United States of America

Donald J Davis