International Business Machines Corporation

Donald George Grice

Eric Eugene Retter

Peter Michael Kogge

James Warren Dieffenderfer

Paul Amba Wilkinson

David B Rolfe

Michael C Dapp

Thomas Norman Barker

Nicholas Jerome Schoonover

Billy J Knowles

Vincent John Smoral

Clive Allan Collins

Richard Edward Nier

Robert Reist Richardson

Donald Michael Lesmeister

Richard Ernest Miles

James Robert Stupp

David Christopher Kuchinski

Howard Thomas Olnowich

Arnold Weinberger

Arthur Robert Williams

Jack E Bresenham

Frank E Howley

David Christoper Kuchinski

David F Johnson

Shing-Chou Pi

An asynchronous switching apparatus is enabled to reshape data pulses and eliminate skewing problems as data is transmitted through the switch. The switching apparatus still functions asynchronously and maintains all the advantages of asynchronous operation, such as, not requiring the alignment and distribution of a central clock, having no central point failure mechanisms, and allowing each node of the parallel system to function free of synchronization requirements with other nodes.

Dynamic routing switch apparatus with clocked signal regeneration

A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Advanced parallel array processor (APAP)

A new bus permits processing elements (PE's) to communicate with other PE's entirely under the control of each PE without a separate bus controller. Each PE has means for broadcasting its priority code on a contention portion of the bus and for sampling the bus after a delay in which it has received the codes from other PE's. Each PE holds its priority code on the bus for a further delay during which other PE's can sample the priority code. The PE's resolve contention for access to the information portion of the bus in a multi stage contention sequence. System usage, made possible by peer-to-peer distribution of bus access control, includes dynamic driven priority schemes, a variety of operating modes and hence flexible multiplexing of message traffic.

Data processing system bus for multiple independent users

An improved method and apparatus are disclosed for generating circular arcs of any arc length greater than zero up to and including a full circle of 360 degrees. The method and apparatus can locate nonsymmetrical closest points for noninteger radius and arc center values. The method and apparatus is capable of generating the incremental move commands for drawing an arc either in the clockwise or counter clockwise direction which is a distinct advantage when used to drive a pen type electromechanical plotter. By dividing the generation of a 360 degree arc into eight octants, only two of the original eight directions need to be considered as candidate directions toward the next integer display matrix value to be displayed. The method and apparatus employ a novel initialization which provides a simple stopping test for any circular arc of arbitrary length and direction. Only simple addition and sign testing is used to display the circular arc.

Bi-directional display of circular arcs

This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two bit decoder for receiving each like order pairs of digits A.sub.i, B.sub.i of two n digit binary numbers A.sub.0, A.sub.1....A.sub.n-1 and B.sub.0, B.sub.1....B.sub.n-1 plus a carry C.sub.in. The decoders generate an output signal called a min term on a different line for each of the four possible combinations A.sub.i B.sub.i, A.sub.i B.sub.i, A.sub.i B.sub.i and A.sub.i B.sub.i of the true and complement of each pair. The min terms from the decoders are fed to an array called the product term generator or AND array which generates product terms

Programmable logic array adder

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Kingston, NY, United States of America

Donald George Grice