Lsi Logic Corporation

Lsi Corporation

Donald Gabrielson

Jonathan W Byrn

Steven Mark Emerson

Gary Michael Lippert

John Emery Nordman

Todd Jason Youngman

James Arnold Jensen

Michael A MInter

Roy Perrigo

A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.

Method for abstraction of manufacturing test access and control ports to support automated RTL manufacturing test insertion flow for reusable modules

A tool for facilitating automatic test pin assignment for a programmable platform device including a process for collecting information related to the programmable platform device, a process for automatically initializing a test pin assignment for the programmable platform device, a process configured to receive user specifications for IOs and a process for performing dynamic test pin reassignment in response to the user specifications.

System for performing automatic test pin assignment for a programmable device

The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration ('test backplane') for all IP blocks is created and loaded into a tool suite. When a user issues a request to consume some IP blocks, the request may be checked for legality within the 'test backplane'. If a test resource (IP block) is not available for activation, then either the test resource may not be activated or the conflicting resource problem must be resolved so that the test resource may be activated. This may avoid late design surprises. The resources on the platform may already have test structures associated with them. All of these test structures may be associated with the &#x201c;test backplane&#x201d;. These pre-exiting test structures may then be connected.

Method and apparatus for automatically configuring and/or inserting chip resources for manufacturing tests

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Rochester, MN, United States of America

Donald Gabrielson