Ncr Corporation

Donald G Tipon

Ikuo J Sanwo

Donald K Lauffer

Gregory Howard Milby

P Keith Muller

Gary Lee Boggs

Robert Samuel Cooper

Chinh Kim Nguyen

Douglas Edward Hundley

Steven Jeffrey Schlesinger

James A Donahue

Gene Robert Erickson

Curtis Hall Stehley

Mehdi H Sani

Chinh V Tran

Jan P Stubbs

Darrin J Marshall

An enhanced ATM switch with CPU node interconnect functionality and peripheral interconnect functionality and network functionality. The ATM switch provides low latency transfer between computer nodes and performs input/output operations with peripherals through the ATM network. SCSI Fibre Channel protocol (FCP) commands are implemented according to ATM standards to provide communication with peripherals. A segmentation and reassembly (SAR) unit is provided for performing ATM segmentation and reassembly. The SAR includes functional units which allow direct connection of an application agent to the core of the switch once the cell characteristics are determined by the application agent and provides ATM cell translation to and from available kernel buffers. The transmission media in the ATM network comprises digital optical links. The enhanced ATM switch may also include a synchronous optical network (SONET) interface for providing SONET transmission over the digital optical links in the ATM network.

ATM/SONET network enhanced as a universal computer system interconnect

A system for verifying design of a digital system. A digital system, which receives input vectors and produces output vectors, is simulated. The invention generates a sequence of synthesized input vectors, and applies them to the simulated system. These input vectors cause changes in internal variables, and the output vectors. The invention also independently computes the values which internal variables and output vectors are expected to assume. The invention then compares the simulated internal and output variables with the computed values. If they agree, the simulation is assumed to function properly.

Automated verification of digital design

In a high speed digital computer data transfer system, a data bus driver, implemented using complementary metal-oxide-semiconductor (CMOS), reduces data bus voltage swings between logic high and logic low levels by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. Voltage overshoot and undershoot of the reduced bus logic levels are prevented by two 'clamping diode' transistors. One of the two clamping diodes connected to the data bus is biased to a point just below conductivity, while the second clamping diode is biased to a point just below conductivity. As a result, if the output voltage rises above a selected level, the first clamping transistor acts as a conducting diode to pull the output voltage down, and, in a similar manner, if the output voltage at node falls below a selected level, then the second clamping transistor functions as a conducting diode to pull the output voltage up to an acceptable level.

CMOS low output voltage bus driver with controlled clamps

In a high speed digital computer data transfer system, a data bus driver reduces data bus voltage swings between logic high and logic low levels by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. Positive and negative overshoot of the reduced bus logic levels are prevented by 'clamping diode' transistors. The data bus driver assumes a tri-state mode when not transmitting data, during which the clamping diode transistors also eliminate positive and negative bus voltage overshoot. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

CMOS low output voltage bus driver

In a pipeline data processing system, a method for additively converting an address expressed in offset form to a corresponding real address in main memory (assuming that such address exists in main memory). Because of the pipeline data processing design, this offset address can be accessed from main memory in the same amount of time required by a non-offset, real address. An apparatus for practicing this method is also provided. This method and apparatus will perform the functions usually performed by a translation table or similar device in virtual memory systems. Furthermore, it will perform those functions faster and will utilize a smaller integrated circuit area than translation table type virtual memory systems.

Method and apparatus for offset register address accessing

A CMOS inverter circuit is coupled to a power source by a cut-off circuit which prevents current flow through the CMOS inverter circuit when the input signal to the CMOS inverter is of a first bi-level state. The cut-off circuit responds to the output signal from a second inverter circuit that is connected to receive the output of the CMOS inverter circuit. A second embodiment of the invention provides a latching function by connecting a feedback path from the output of the second inverter circuit to a toggle gate circuit connected to the input to said CMOS inverter circuit.

MOS no-leak circuit

A MOS circuit for trimming a digital pulse signal by delaying the rising edge of the pulse signal for a predetermined period of time and passing the falling edge without delay. The circuit includes two MOS output transistors and a signal buffer. The signal buffer has a number of stages for delaying the pulse signal, with the number chosen to control the delay in the rising edge of the pulse signal. One of the output transistors receives the pulse signal at its drain and is enabled by the delayed pulse signal from the signal buffer to pass the pulse signal after the predetermined period of time to its source at the output of the circuit, so that the rising edge is delayed, but the falling edge is not. The other output transistor is enabled to ground the output of the circuit after the falling edge of the pulse signal. A self-booting circuit drives the gate of the one output transistor to assure that the voltage level of the trimmed signal will not be reduced by dissipation across the transistor.

Signal edge trimmer circuit

Apparatus and method for removably mounting an integrated circuit package having a plurality of electrical pins wherein a plurality of mating pins each having a receptacle filled with liquid mercury are connected to the electrical pins of the integrated circuit package and the temperature reduced such that the liquid mercury solidifies thereby firmly bonding the electrical pins together. The assembly may be inserted into a Dewar type vessel and covered with a low temperature liquified gas for the dual purpose of solidfying the liquid mercury and cooling the integrated circuit package.

Cryogenic packaging scheme

The circuit of the present invention converts CMOS logic level signals to corresponding ECL logic level signals to permit the coupling of CMOS and ECL devices. In addition, the present invention maintains a relatively constant impedance as the logic levels on its output change. The circuit has an input terminal connectable to a source of a first set of logic signals and an output terminal connectable to a device that is responsive to a second set of logic level signals. First and second power terminals are provided for connection to first and second power supplies, respectively. A transistor of first conductivity type having first, second and gate terminals is provided with the gate terminal connected to the input terminal and the first terminal connected to the first power supply terminal. A second transistor of opposite conductivity type having a first, second and gate terminal is provided with the gate terminal of the second transistor connected to the second terminal of the first transistor. The second terminal of the second transistor is connected to the output terminal and the first terminal of the second transistor is connected to the second power supply terminal. A saturation means is connected between the gate terminal and the second terminal of the second transistor. The saturation means is responsive to the signal on the input terminal for saturating the second transistor in an 'ON' state when the logic level 0 is applied to the input terminal.

CMOS to ECL converter-buffer

The circuits of the present invention convert CMOS logic levels to corresponding ECL logic levels to permit the coupling of CMOS and ECL circuits. One preferred circuit embodiment is comprised of three p-channel transistors and one n-channel transistor. The first p-transistor has its source connected to a reference potential, such as ground, and its drain electrode connected to the source of the second p-transistor. The drain and the gate of the second p-transistor are connected together to an output terminal. The drain of the third p-transistor is connected to the output terminal. The gate and the source of the third p-transistor are connected to the drain of the n-transistor. The source of the n-transistor is connected to a CMOS compatible potential source. The CMOS logic level signal is coupled to the gate of the first p-transistor and the gate of the n-transistor. The output terminal is connected to an ECL compatible potential source via a termination resistor. Two other circuit embodiments are disclosed which provide for non-inverted and inverted outputs.

CMOS to ECL interface circuit

A data processing system having optically linked subsystems, including an optical keyboard. The optical keyboard includes sequentially strobed LED's arranged to provide intersecting light paths in an X-Y matrix. A key on the keyboard is associated with each intersection of the light paths. When the key is depressed, the optical signals on the intersecting light paths are blocked. The resulting coded optical signals are used directly in transmitting to another subsystem the data entered at the keyboard.

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San Diego, CA, United States of America

Donald G Tipon