Hamilton Sundstrand Corporation

Sundstrand Corporation

Other

Donald G Kilroy

Wayne H Oldenburg

John A Dickey

Nicholas J Robertson

Robert C Cooney

Michael J Hanson

John F Defenbaugh

Josef Maier

Shan-Chin Tsai

Bruce D Beneditz

Christian Miller

Josh C Swenson

Frank J Ludicky

Thomas Doubek

Scott D Arthur

Bernd Löfflad

Scott R Myers

Bernd Lofflad

A system balances current flowing through a solid-state power controller system including at least two output channels connected in parallel. The system delivers a first current to a load via a first output channel to a load, and delivers a second current to the load via a second output channel connected in parallel with the first output channel. The system further determines a first strength of the first current and a second strength of the second current, and adjusts at least one of a first resistance of the first output channel and a second resistance of the second output channel such that the first current strength is substantially equal to the second current strength.

Multi-channel current balancing system including parallel solid-state power controllers

Embodiments are directed to a transient protection circuit configured for use in a SSPC having a plurality of power channels. The transient protection circuit includes a shared transient voltage suppressor, and a shared protection line communicatively coupled to the shared transient voltage suppressor. The shared protection line is configured to be communicatively coupled to and shared by the plurality of power channels. When the shared protection line is communicatively coupled to and shared by the plurality of power channels, energy above a threshold on any one of the plurality of power channels is dissipated through the shared protection line and the shared transient voltage suppressor.

Transient voltage suppressor having built-in-test capability for solid state power controllers

A method of containing arc faults in a power distribution unit includes in response to a bus bar temperature exceeding a bus bar temperature threshold, thermally opening a conductive element extending between an energizing coil of a contactor, a bus bar, and a controller. The controller is configured to selectively open and close the contactor. The conductive element is electrically connected to the energizing coil of the contactor and the controller. The conductive element is electrically isolated from a power source electrically connected to the first bus bar through the contactor.

Power distribution unit and method of containing arc faults in power distribution units

A lightning protection circuit includes a transistor array, a transistor array gate drive, and a second stage protection element which forces a voltage at the gate node of the transistor array to be higher than the voltage at the source node of the transistor array when a threshold is exceeded.

Two-level lightning protection circuit

A DC arc fault device and methodology includes acquiring a signal in response to a DC current. A software module identifies a parallel DC arc event when a difference between a maximum signal value and a minimum signal value exceeds a threshold. The software module also determines average signal values over multiple selected time periods and identifies a series DC arc event in response to the difference between the average values exceeding a predetermined threshold.

DC arc fault detection and protection

Transient overvoltage suppression circuit prevents voltage surges from damaging an attached load. The suppression circuit includes a transistor connected in series with a low-side or return line of the load. A control circuit monitors the voltage on the input line (i.e., high-side) and in response to a detected voltage transient turns the transistor OFF to isolate the load from the transient voltage.

System and method to provide transient overvoltage suppression

An electrical fault locating system for distributing power from an input to a plurality of output channels provides fault detection and locating for each of the plurality of output channels. Each of the plurality of output channels is monitored by a fault detection circuit to detect the presence of an electrical fault. In response to a detected fault condition, the fault detection circuit isolates the output channel from the input and generates an output identifying the output channel on which the fault was detected. A fault locating device injects a high-frequency (HF) signal onto the input of the electrical system, the HF signal is distributed to each of the plurality of output channels, and the monitored reflection of the HF signal is monitored by the fault locating device to calculate a distance to the detected fault. The distance calculated by the fault locating device is combined with the channel identification provided by the fault detection circuit to generate a specific location associated with the detected fault.

Wire fault locating in distributed power systems

An AC arc fault device and methodology includes acquiring a signal in response to an AC current and defining overcurrent regions that correspond to the alternating directions of the AC current and a normal region. A software module identifies a parallel AC arc event over a selected time period in response to multiple occurrences of the acquired signal moving into one of the overcurrent regions. The software module also determines average current values over multiple selected time periods and identifies a series AC arc event in response to the difference between the average values exceeding a pre-determined threshold.

AC arc fault detection and protection

An apparatus and method for protecting an AC load from half-wave rectified power detects a half-wave rectified voltage or current, sets a status indication indicating the type of asymmetric fault causing the half-wave rectified power, and selectively turns the SSPC ON or OFF depending on the type of fault. There are two example circumstances that can cause an asymmetric fault: when the SSPC is OFF and a switch is shorted ('SSPC Failed Shorted'), or when the SSPC is commanded ON and a switch remains open ('SSPC Failed Open'). If the SSPC is OFF when the half-wave rectified AC voltage or current is detected, an &#x201c;SSPC Failed Shorted&#x201d; status indication is set, and the SSPC is turned ON to clear the fault. If the SSPC is commanded ON when the half-wave rectified AC voltage or current is detected, an &#x201c;SSPC Failed Open&#x201d; status indication is set, and the SSPC is turned OFF to clear the fault.

Asymmetric fault detection and protection with AC solid state power controllers

An apparatus, and a method of controlling a solid state power controller ('SSPC') selectively allows a current through a solid state power control switch in response to the current in a plurality of SSPCS exceeding at least one threshold. A microprocessor module collects power surge data from a plurality of groups of SSPCs, and determines if the amount of power surge data within a group of SSPCs is sufficient to constitute a lightning threat. If the microprocessor module determines a lightning threat is present, the microprocessor module sends a command to certain SSPCs in the afflicted group to lockout an instantaneous trip protection for the duration of the lightning threat, allowing the power surge to pass from the SSPCs to a load or plurality of loads, leaving the SSPCs undamaged.

Increasing the system stability and lightning capability in a power distribution system that utilizes solid-state power controllers

A method of detecting and indicating a presence of alternating current (AC) series arc fault events in current supplied by an AC electrical power source to an electrical load for the power source comprises the steps of: measuring positive and negative current through the load over a first sample cycle of the AC power to establish first measured positive and first measured negative current levels; determining the absolute value of the first measured positive and first measured negative current levels to establish a first absolute positive current level and a first absolute negative current level; adding the first absolute positive current level and the first absolute negative current level to establish a first sum current level; measuring positive and negative current through the load over a second sample cycle staggered from the first sample cycle to establish second measured positive and second measured negative current levels; determining the absolute value of the second measured positive and second measured negative current levels to establish a second absolute positive current level and a second absolute negative current level; adding the second absolute positive current level and the second absolute negative current level to establish a second sum current level; subtracting the second sum current level from the first sum current level to establish a current difference level; and indicating a series arc fault event if the current difference level exceeds a predetermined threshold level.

Alternating current series arc fault detection method

A method of controlling a solid state power controller includes selectively allowing a transient current through a solid state power control switch in response to the transient current exceeding at least one threshold.

Solid state power controller with lightning protection

A system and method for controlling an electronic circuit breaker prevents the circuit breaker from contributing its own delay to a power interruption time window on a load. A monitor coupled to a control processor in the circuit breaker causes the control processor to operate in a low-energy consumption sleep mode if it detects a power interruption. During the sleep mode, the control processor draws current from an energy storage device until the power source is reconnected to the control processor. Because the control processor operation is suspended rather than stopped during the power interruption, the control processor does not need to conduct any preliminary power up operations when power is resumed.

Power interruption system for electronic circuit breaker

A power transfer control system for use in an AC electric power generation system comprises a generator control unit (GCU) which senses and controls the output of a generator, and a bus power control unit (BPCU) which communicates with the GCU to control and coordinate a power transfer between the generator and another source. Each unit communicates power transfer information, which eliminates the requirement of redundant sensing circuitry and wiring for the BPCU. The BPCU transmits master power control information and a synchronizing signal indicating a zero phase reference point of a control waveform to which the power transfer will take place. The GCU compares parameters of the output power of its respective source with the master power control information and the synchronizing signal. The GCU adjusts its generator's output to track the master power control information, and generates delta phase information representing the phase displacement between said synchronizing signal and the output power of the first source. It also generates a power ready signal when a difference between said sensed parameters of the output power and said master power control information is less than a predetermined threshold. When the BPCU receives this information from the GCU, it initiates a no-break power transfer if the delta phase information is less than a predetermined threshold. The synchronizing signal is sent at a given interval representing the zero crossing at a given frequency of the master waveform. The BPCU may adjust this transmission rate upon variances of the master waveform.

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Rockford, IL, United States of America

Donald G Kilroy