International Business Machines Corporation

Donald G Grice

Daniel James Winarski

Louie Arthur Dickens

Tara Lynn Astigarraga

Peter H Hochschild

Christopher V Derobertis

Jose Roberto Mosqueda Mejia

John Lewars

David B Rolfe

Billy J Knowles

Clive Allan Collins

James Stephen Fields, Jr

Eric Eugene Retter

Rama Krishna Govindaraju

Robert Sidney Blackmore

William Todd Boyd

James Warren Dieffenderfer

John Scott Houston

Piyush Chaudhary

Michael C Dapp

Thomas Norman Barker

George William Daly, Jr

Derrick LeRoy Garmire

Christine M Desnoyers

Leonard W Helmer, Jr

Vincent John Smoral

Richard Edward Nier

Steven J Martin

Donald Michael Lesmeister

Fu Chung Chang

William A Hanson

Jason E Goscinski

Georgy A Chochia

Appoloniel N Tankeh

Peter Kenneth Szwed

Chulho Kim

Peter Michael Kogge

Carl Alfred Bender

Monty Montague Denneau

Paul Amba Wilkinson

Craig Brian Stunkel

Nicholas Jerome Schoonover

Kevin J Gildea

Robert Reist Richardson

Donald W Price

Richard Ernest Miles

Michael Patrick Muhlada

James Robert Stupp

David Christopher Kuchinski

Patricia E Heywood

Donna C Myers

William R Milani

Reza S Raji

Antoinette E Vallone

Vadim M Tsinker

Sheryl M Genco

Thomas K Heller, Jr

Thomas J Heller

Tim Zhang

Methods, systems, and computer program products for data entry device security are provided. Aspects include receiving an indication of a user presence at a data entry device, wherein the data entry device includes a surface with apertures, and wherein the apertures include a material with a reflection coefficient. A presence of a fraud device is determined by emitting, from beneath the surface, security light from a set of one or more emitters, wherein the security light has a security light luminous power. A reflection of the security light off the material is collected by a first set of one or more sensors, wherein the reflection has a reflection luminous power. A luminous power range is determined based on the security light luminous power and the reflection coefficient and based on the reflection luminous power being outside the luminous power range, security measures are engaged at the data entry device.

End user protection against ATM keypad overlay

A capability is provided for predicting the performance of a communications network, such as a multi-stage communications network. The predicted performance includes, in one aspect, predicting the amount of bandwidth that a server of the communications network could deliver with a full load on the network. In one aspect, the predictive capability includes determining an aggregate load for each server of the network being analyzed; performing normalization on the loads of the links used by the servers to obtain updated link and/or server bandwidths; and determining for each server, a minimum bandwidth over the links in the server's route.

Predicting the performance of a multi-stage communications network under load from multiple communicating servers

As disclosed herein, a method, executed by a computer, for analyzing a performance metric includes distributing link connection information for a network to each node in the network, pairing each node with another node in the network to provide paired nodes, testing a performance metric for the paired nodes, and generating a performance report for the network. The method may further include receiving link connection information for the network. The method may further include constructing a connectivity graph based on the received link connection information. The method can be used to test link performance within non-homogeneous networks. A computer system product and a computer program product corresponding to the method are also disclosed herein.

Network performance testing in non-homogeneous networks

As disclosed herein, a method, executed by a computer, for analyzing a performance metric includes distributing link connection information for a network to each node in the network, pairing each node with another node in the network to provide paired nodes, testing a performance metric for the paired nodes, and generating a performance report for the network. The method may further include receiving link connection information for the network. The method may further include constructing a connectivity graph based on the received link connection information. The method can be used to test link performance within non-homogeneous networks.

In remote direct memory access transfers in a multinode data processing system in which the nodes communicate with one another through communication adapters coupled to a switch or network, failures in the nodes or in the communication adapters can produce the phenomenon known as trickle traffic, which is data that has been received from the switch or from the network that is stale but which may have all the signatures of a valid packet data. The present invention addresses the trickle traffic problem in two situations: node failure and adapter failure. In the node failure situation randomly generated keys are used to reestablish connections to the adapter while providing a mechanism for the recognition of stale packets. In the adapter failure situation, a round robin context allocation approach is used with adapter state contexts being provided with state information which helps to identify stale packets.

Failover mechanisms in RDMA operations

In a multinode data processing system in which nodes exchange information over a network or through a switch, a structure and mechanism is provided within the realm of Remote Direct Memory Access (RDMA) operations in which DMA operations are present on one side of the transfer but not the other. On the side in which the transfer is not carried out in DMA fashion, transfer processing is carried out under program control; this is in contrast to the transfer on the DMA side which is characteristically carried out in hardware. Usage of these combination processes is useful in programming situations where RDMA is carried out to or from contiguous locations in memory on one side and where memory locations on the other side is noncontiguous. This split mode of transfer is provided both for read and for write operations.

Half RDMA and half FIFO operations

A method of interfacing two components of a computing system is provided wherein the method includes providing a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of the computing system and a slave bus controller of a processor unit of the computing system. The method also includes providing means for transmitting a command packet with an address associated with data pertaining to the command from the master bus controller to the slave bus controller. In addition, the method includes providing means for determining by the slave bus controller whether the slave bus controller can accept the command. The method further includes providing means for transmitting an acknowledgement from the slave bus controller to the master bus controller after the slave bus controller receives a first signaling interval for the command packet if the slave bus controller can accept the command packet.

Method and system for interfacing components of a computing system with a pair of unidirectional, point-to-point buses

Method for interfacing components of a computing system with a pair of unidirectional, point-to-point buses

Received portion of message is stored persistently and transmitted without awaiting receipt of another portion of the message and without generating a new message. The storing and transmitting can occur substantially simultaneously and be performed by one or more hardware elements. Originator of the message can choose whether to indicate indication of broadcasting of the message. First hardware element can determine local acknowledgement for message and second hardware element can determine determinative signal of the local acknowledgement and at least one of: one or more collected intended recipient acknowledgements for the message; and one or more collected determinative signals of intended recipient acknowledgements for the message.

Parallel computer network broadcasting and acknowledgement

A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper. Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge. Data passes into the network or out of the network through the edge when it is active, and the coupling permits dispersal of data entering the network or collection of data leaving the network such that the data rate through the edge matches both the sustained and peak data rates of the system external to the network.

Advanced parallel array processor I/O connection

A method and system for synchronizing allocation of resources in a parallel processing system. At predefined time intervals, each user application executing in a parallel processing system is given a higher priority such that the system resources are allocated to the user applications instead of the operating system services. This high priority lasts for a predetermined amount of time. When the time has elapsed, each priority value is lowered, thus giving the operating system services an opportunity to execute.

Resource allocation synchronization in a parallel processing system

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New Paltz, NY, United States of America

Donald G Grice