Ncr Corporation

Donald G Craycraft

Giao N Pham

William E Coleman

George C Lockwood

Herman Albertine, Jr

Darrel D Donaldson

James F Patella

A sense amplifier for a read only memory array which is formed from a multiplicity of NAND organized FET stacks. The sense amplifier compares the current sinking capacity of a selected bit line stack with that of a reference stackline, the difference being detected as a voltage shift in a differential stage. Pass FETs with gate electrodes biased in inverse proportion to the bit and reference line potentials are serially connected between the corresponding lines and reference nodes.

Current sinking responsive MOS sense amplifier

A field effect transistor driver circuit figured to have different rates of change of the output signal depending on fabrication mask designation of selected transistors to be either depletion or enhancement type devices.

FET driver circuit with mask programmable transition rates

A read-only memory array formed from a multiplicity of NAND-organized FET stacks which are arranged in pairs and connected in alternate succession of adjacent pairs at opposite ends. Selection of stacks by pairs is performed by connecting the common node of four stacks at one end to a bit line and the common node of another four stacks, only two being common with the former four stacks, to ground potential. Selection between adjacent stack pairs is performed by bank select FETs in each stack. Each stack is precharged at both ends prior to selection. A sense amp is utilized to compare the current sinking capacity of the selected bit line with a reference stack, the difference being detected in a differential amplifier. A programmable output driver provides an adjustable rate of change in the output signal for step input signals.

X-and-OR memory array

A comparator circuit suitably configured and synchronously operated to distinguish between the levels of two input signals and to provide the relative standing of the levels in binary format. In one form, a symmetrically organized circuit having the fundamental structure of a bistable multivibrator is initially operated in a differential mode and subsequently transitioned to a latch mode. Appropriate constant current source biasing shifts the differential mode operation to optimize amplifier element gain characteristics for the levels of input signals received. The amplified difference between the two input signals is stored within various capacitive elements of the circuit output stages. During the differential mode, the bistable multivibrator cross-coupling elements are disabled. At the termination of the differential mode, the amplified difference between the two input signals provides the initial conditions for the regenerative dynamics associated with the onset of cross-coupling and the transition to the latched state. Preferably, the input signals and the bias circuit are disabled in synchronism with the cross-coupling operation, to provide a stable output from the multivibrator circuit in conventional binary format.

MOS Sense amplifier

A volatile/non-volatile RAM cell employing a bistable multivibrator with non-volatile, alterable-threshold capacitors coupled to the output terminals thereof to provide backup data storage in a power-down situation. In one embodiment, the non-volatile capacitors each have a non-alterable section and an alterable section, the non-alterable section having either a depletion or an enhancement threshold. The V/NV RAM cell employs a pair of field effect transistors of depletion or enhancement type to couple the non-volatile capacitors to the output terminals. These coupling transistors form with the non-volatile capacitors a pair of nodes. The coupling transistors are biased such that a write voltage signal applied to the gates of the non-volatile capacitors produces a bootstrapped voltage on one of the pair of nodes which is effectively isolated from the output terminals of the cell.

Static volatile/non-volatile ram cell

An FET read-only memory cell capable of storing more than one bit per cell. The channel geometry of the FET cell is selected to provide an electrical output that is characteristic of a predetermined combination of bits. For example, the FET channel width can be selected to provide one of 2.sup.n predetermined output voltage values which correspond to the 2.sup.n possible arrangements of n bits. The read function utilizes 2.sup.n -1 sense amplifiers, which are connected to the FET. Each sense amplifier is selectively activated at a separate one of 2.sup.n -1 voltage levels which is intermediate two adjacent values of the 2.sup.n output voltages. The collective outputs of the sense amplifiers drive a logic circuit for decoding the values of the n data bits represented by the FET channel width.

ROM memory cell with 2.sup.n FET channel widths

A plasma charge display device having a channel containing an ionizable medium with the channel defining an endless length as in the case of a circular channel. At least one input electrode is located in a first position, and transfer electrodes extend away from the input electrode on opposite sides thereof completely along the length of the channel. Gas ionization results in the formation and shifting of light emitting areas in either direction relative to the position of the input electrode. The transfer electrode positions are related to the input electrode position in a manner such that the light emitting areas can be shifted through the position of the input electrode from one side to the other thereof.

Circular plasma charge display device

A system for loading a plasma charge transfer device and for holding charges applied thereto. Input and transfer electrodes are positioned on opposing walls which define a channel confining an ionizable medium. The electrodes are arranged for the application of potential differences between adjacent electrodes whereby the charges may be shifted away from the input electrode to a desired location and in a desired pattern along the length of the device. The charges are then held at the desired location by applying potential differences in a fashion such that the charge is circulated between a set of at least four sequentially positioned transfer electrodes at the desired holding location.

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Spring Valley, OH, United States of America

Donald G Craycraft