International Business Machines Corporation

Donald G Chesebro

Mark Alan Lavin

Daniel Nelson Maynard

Young O Kim

Robert W Sweetser

Francis J Soychak

An efficient method for modifying a chip or package design allows for the creation of small shapes without excessive expansion of design data. A computer program takes a physical design, represented in a computer data file, and generates a modified version of the design in which fill shapes have been added. Subsequently, when the modified design is processed, the resulting semiconductor chip or package will contain physical images of the added fill shapes, with the effect of making local pattern density more uniform and hence reducing process-induced variations in feature size and shape.

Efficient generation of fill shapes for chips and packages

A method of enhancing first order alignment marks formed in the respective layers of a processed semiconductor wafer in which critical masking steps are carried out. After a given mark is formed, it is tested for visual contrast. If the contrast is insufficient to provide adequate alignment, a block mask is formed on the critical mask. The block mask exposes all of the alignment target areas and protects the product regions of the wafer, and the critical mask only exposes the mark to be enhanced. The mark is then etched for a time period which is a function of the measured visual contrast. This method of selectively enhancing selected ones of the first order alignment marks greatly enhances the utility of such marks, increasing the accuracy of critical masking steps.

Visibility enhancement of first order alignment marks

A method is provided for making a semiconductor device which includes the steps of forming a first insulating layer on the surface of a semiconductor layer having a given conductivity type, forming an opening in the insulating layer and forming a diffusion region of a conductivity type opposite to that of the given conductivity type at the surface of the semiconductor layer to provide a P-N junction below the surface of the semiconductor layer. A trench is then formed along a given axis in the semiconductor layer having a sidewall passing through the opening and through the P-N junction. A second layer of insulation is formed on the sidewall of the trench, on the first insulating layer and through the opening onto the diffusion region. The second layer of insulation is etched in the direction of the given axis until substantially all of the second layer of the insulation is removed from the opening, and an electrical contact is formed on the diffusion region within the opening. In a preferred embodiment of the invention, the second layer is a dual insulating layer which may include a layer of silicon dioxide grown on the semiconductor layer and a layer of silicon nitride deposited on the layer of silicon dioxide.

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Colchester, VT, United States of America

Donald G Chesebro