International Business Machines Corporation

Globalfoundries Inc.

Donald Francis Canaperi

Son Van Nguyen

Mahadevaiyer Krishnan

Hosadurga K Shobha

Deepika Priyadarshini

Alfred Grill

Fee Li Lie

Kevin Shawn Petrarca

Alexander Reznicek

Takeshi Nogami

Zhenxing Bi

Thamarai Selvi Devarajan

Matthew T Shoudy

Kangguo Cheng

Lawrence Alfred Clevenger

Sanjay C Mehta

Richard Paul Volant

Kamal Kumar Sikka

Dario Leonardo Goldfarb

Raghuveer Reddy Patlolla

Kenneth Jay Stein

Daniel A Corliss

Dinesh Gupta

Shawn Peter Fetterolf

Chih-Chao Yang

Peng Xu

Daniel C Edelstein

Sivananda K Kanakasabapathy

Thomas J Haigh, Jr

Cornelius Brown Peethala

Michael F Lofaro

Michael Straight Hibbs

Miaomiao Wang

Rangarajan Jagannathan

Steven Erik Steen

Rebecca D Mih

William C Wille

James Anthony Tornello

Nicolas J Loubet

Michael Rizzolo

Sampath Purushothaman

Benjamin David Briggs

Timothy Joseph Dalton

Jack Oon Chu

Stephen McConnell Gates

Eric R Miller

John Albrecht Ott

Richard Anthony Conti

John Christopher Arnold

Eric Jeffrey White

Wei Lin

Spyridon Skordas

William J Cote

Darryl D Restaino

Satya Venkata Nitta

Judith Marie Rubino

James Edward Fluegel

Richard O Henry

David Angell

Ali Khakifirooz

Theodorus E Standaert

Keith E Fogel

Guy M Cohen

Subramanian Srikanteswara Iyer

Thomas N Adam

Xunyuan Zhang

Ashim Dutta

Jon Alfred Casey

Muthumanickam Sankarapandian

David Lee Rath

Sean Teehan

Hon-Sum Philip Wong

Eric D Perfecto

Shidong Li

James John Kelly

David Noel Light

Raymond R Horton

Max Gerald Levy

Raghavasimhan Sreenivasan

Christopher Peter D'Emic

Troy Lawrence Graves-Abe

Matthew J Sendelbach

Dominik Metzler

Joyce C Liu

Leena Paivikki Buchwalter

Huy Cao

Clifford Owen Morgan, Iii

Paul M Feeney

Charan Veera Venkata Satya Surisetty

Prasad Bhosale

Mona Abdulkhaleg Ebrish

Kenneth M Davis

Perminder S Bindra

Michael Berger

Kunaljeet Tanwar

Scott Alan Estes

Michael T Brigham

Terrance M Wright

Michael A Cobb

Philip Murphy

3D nanochannel interleaved devices for molecular manipulation are provided. In one aspect, a method of forming a device includes: forming a pattern on a substrate of alternating mandrels and spacers alongside the mandrels; selectively removing the mandrels from a front portion of the pattern forming gaps between the spacers; selectively removing the spacers from a back portion of the pattern forming gaps between the mandrels; filling i) the gaps between the spacers with a conductor to form first electrodes and ii) the gaps between the mandrels with the conductor to form second electrodes; and etching the mandrels and the spacers in a central portion of the pattern to form a channel (e.g., a nanochannel) between the first electrodes and the second electrodes, wherein the first electrodes and the second electrodes are offset from one another across the channel, i.e., interleaved. A device formed by the method is also provided.

3D nanochannel interleaved devices

Fabrication method for forming a resistance tunable fuse stack structure includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer, a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting at least one of the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse contacts.

Resistance tunable fuse structure formed by embedded thin metal layers

A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.

Surface conversion in chemical mechanical polishing

A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.

Nano multilayer carbon-rich low-k spacer

A method of fabricating a dielectric film includes depositing a first precursor on a substrate. The first precursor includes a cyclic carbosiloxane group comprising a six-membered ring. The method also includes depositing a second precursor on the substrate. The first precursor and the second precursor form a preliminary film on the substrate, and the second precursor includes silicon, carbon, and hydrogen. The method further includes exposing the preliminary film to energy from an energy source to form a porous dielectric film.

Forming high carbon content flowable dielectric film with low processing damage

A method of manipulating a molecule having a dipole moment is provided. A non-limiting example of the method includes providing an array of electrodes with each respective electrode in electrical communication with a respective interconnect. Each respective electrode is individually addressable through its respective interconnect, and each respective electrode is capable of generating an electromagnetic field when stimulated. The method provides the molecule above the array of electrodes and stimulates one or more electrodes within the array of electrodes to manipulate the molecule.

Manipulation of a molecule using dipole moments

A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse contacts in the fuse stack structure.

Methods for forming an integrated circuit are provided. Aspects include providing a wafer substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure, the memory area interconnect structure comprising metal interconnects formed within a first interlayer dielectric, recessing a portion of the memory area interconnect structure, forming a bottom electrode contact on the recessed portion of the memory area interconnect structure, forming a bottom electrode over the bottom electrode contact, forming a protective dielectric layer over the non-memory area interconnect structure, and forming memory element stack layers on a portion of the bottom electrode.

Embedded MRAM device formation with self-aligned dielectric cap

Techniques regarding self-sterilizing touch sensors are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a heating element. Also, the apparatus can comprise a protective layer adjacent to the heating element. The heating element can generate heat based on a pressure applied to the protective layer and can sterilize the protective layer.

Self-sterilizing sensor

A stacked semiconductor microcooler includes a first and second semiconductor microcooler. Each microcooler includes silicon fins extending from a silicon substrate. A metal layer may be formed upon the fins. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.

Semiconductor microcooler

A semiconductor structure is provided. A non-limiting example of the structure includes a substrate and a plurality of first pillars of a conductive material above a first portion of the substrate. The structure further includes a plurality of second pillars of the conductive material above a second portion of the substrate, wherein the plurality of first pillars are offset by a gap distance from the plurality of second pillars along a longitudinal axis.

Interleaved structure for molecular manipulation

A stacked semiconductor microcooler includes a first microcooler and a second microcooler. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant.

A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.

Semiconductor structures of more uniform thickness

Magnetic tunnel junction pillars are encapsulated by an oxidized diffusion barrier layer. Oxygen within the encapsulating material is used to oxidize metallic residue outside the pillars, converting the residue to a non-conductive material such as a metal oxide or metal oxynitride. Selective deposition of manganese on the metal layers of the pillars can be followed by oxidation of the manganese to form a manganese oxide diffusion barrier. Alternatively, manganese deposition can be followed by deposition of silicon dioxide and subsequent annealing to form a manganese silicate diffusion barrier.

Dual function magnetic tunnel junction pillar encapsulation

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Bridgewater, CT, United States of America

Donald Francis Canaperi