Intel Corporation

Digital Equipment Corporation

Donald F Hooper

Gilbert M Wolrich

Matthew James Adiletta

Debra Bernstein

William Ralph Wheeler

Mark B Rosenbluth

Snehamay Kundu

James D Guilford

Myles Wilde

Sanjeev Jain

Richard D Muratori

Michael F Fallon

Suresh S Kalkunte

Serge Kornfeld

Desmond R Johnson

Peter C Bixby

Matthew S Goldman

Stephanie L Hirnak

Suban Krishnamoorthy

Eric Walker

David M Tongel

Alok Kumar

Aaron Gorius

Uday Ramakrishna Naik

Hugh Wilkinson

Robert E Stewart

Peter J Barry

Michael B Evans

David B Fite, Jr

Hugh M Wilkinson, Iii

Matthew I Adiletta

Robert P Ottavi

David Romano

Eswar Eduri

Robert J Kushlis

Praveen B Mosur

James L Finnerty

Dennis Rivard

David F Wall

Edward G Fortmiller

Lai-Wah Hui

Dave M Tongel

Jay S Newcomb

John C Cole

Douglass Carrigan

Chandra Vora

A system apparatus and method for supporting one or more functions in an IO virtualization environment. One or more threads are dynamically associated with, and executing on behalf of, one or more functions in a device.

Dynamic association and disassociation of threads to device functions based on requestor identification

A parallel hardware-based multithreaded processor. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread.

Register set used in multithreaded parallel processor architecture

A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads&#x2014;one for header segment processing and the other for handling payload segment(s)&#x2014;or a different program thread for segment of data in a packet. Dedicated inputs for ready status and sequence numbers provide assistance needed for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.

Method and apparatus for gigabit packet assignment for multithreaded packet processing

In accordance with one exemplary embodiment, the present disclosure includes a method for executing application software during a simulation that models a processor for which the application software was developed. The method may include capturing results of the simulation to produce a simulation history. The method may also include providing a graphical user interface (GUI) that includes one or more cross-linked packet-centric views of the simulation history for packets operated on by the application software during the simulation. The cross-linked packet-centric views may include a packet status list GUI, a packet event list GUI, a packet dataflow GUI, a thread list GUI, and a thread history GUI. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Graphical user interface for use during processor simulation

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD. . . THREAD). The processor maintains execution threads (THREAD. . . THREAD) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD. . . THREAD).

Method and apparatus to support a large Internet Protocol Forwarding Information Base. A packet is received at a network device, the packet including a destination address. A table is indexed into using a portion of the destination address to locate an entry in the table associated with the portion of the destination address. A pool index is derived from the portion of the destination address and is used to identify a pool of data blocks from among a plurality of pools of data blocks. The entry and the pool of data blocks are navigated to find a next-hop for the packet.

Method and apparatus to support a large internet protocol forwarding information base

A method of processing network data in a network processor includes assigning a group of receive threads to process network data from a port. Each of the group of receive threads process network data in a round-robin fashion.

Multi-threaded round-robin receive for fast network port

In general, in one aspect, the disclosure describes a method that includes at a first packet processing thread executing at a first core, performing a memory read to data shared between packet processing threads including the first thread. The method also includes at the first packet processing thread, determining whether the data returned by the memory read has been changed by a packet processing thread operating on another core before performing an exclusive operation on the shared data by the first packet processing thread.

Providing access to data shared by packet processing threads

A system and method for controlling transmission of cells is described. The cells are associated with virtual circuits that either require shaping according to constant bit rate (CBR) or real-time variable bit rate (rt-VBR), or no shaping with transmit selection based on priority (for services other than CBR and rt-VBR). The system transmits the shaped and unshaped traffic using one or more circular control structures. The control structures have time slots at the granularity of the maximum system transmit rate.

Scheduling system for transmission of cells to ATM virtual circuits and DSL ports

A device and method for processing a data packet at a device are described. The device receives data packets and determines available memory in one or more of local memories of a plurality of execution threads. The device stores packet information in an available one of the local memories of the execution threads.

Processing a data packet

A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divided among phases, and each of the data units processed by a thread is processed by a different one of the phases.

Phasing for a multi-threaded network processor

Providing flow control includes receiving at a router an indication of the ability of each one of multiple ports not directly connected to the router to receive data from the router and controlling transmission of data from the router to the multiple ports based at least on the indication.

Flow control in a network environment

A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet is presented. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.

Multi-threaded sequenced receive for fast network port stream of packets

A processor such as a parallel hardware-based multithreaded processor () is described. The processor () can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified bit of a register () being set or cleared and which specifies which bit of the specified register to use as a branch control bit.

Branch instruction for processor with branching dependent on a specified bit in a register

In general, in one aspect, the disclosure describes a technique of determining forwarding information for at least a sub-set of members of a multi cast group, and sending, toward a downstream entity, at most a single copy of data to be multicasted to the sub-set of members and the determined forwarding information.

Network multicasting

Growing community of inventors

Shrewsbury, MA, United States of America

Donald F Hooper