Texas Instruments Corporation

Cisco Technology, Inc.

Cisco Systems Inc.

Donald Edward Steiss

Jonathan H Shiell

Earl T Cohen

Timothy David Anderson

Mihir Narendra Mody

John Joseph Williams, Jr

John Andrew Fingerhut

Arthur John Redfern

Charles Lance Fuoco

David J Hoyle

Sriramakrishnan Govindarajan

Frank L Laczko, Sr

Gregory Raymond Shurtz

Joel J Graber

Jonathan Elliot Bergsagel

Kai Chirca

Tuan Q Dao

Clive D Bittlestone

John H W Bettink

Sanjive Agarwala

William Norman Eatherton

John M Johnsen

Steven D Krueger

Anthony Martin Hill

Laurence Ray Simar, Jr

John C Carney

Jason A T Jones

Henry M Darley

Jonathan Rosen

Marvin Wayne Martinez, Jr

Barry Scott Burns

Mark Warden Hervin

Douglas J Matzke

Peter Cumming

James O Bondi

Tarek Aziz Lahlou

Christopher E White

Christopher Barr

Maria B Hipona

Jason At Jones

John Williams

John J Williams

Will Eatherton

Zheng Zhu

Richard P Wiley

Andy Fingerhut

In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

Real time input/output address translation for virtualized systems

A reconfigurable matrix multiplier (RMM) system/method allowing tight or loose coupling to supervisory control processor application control logic (ACL) in a system-on-a-chip (SOC) environment is disclosed. The RMM provides for C=A*B matrix multiplication operations having A-multiplier-matrix (AMM), B-multiplicand-matrix (BMM), and C-product-matrix (CPM), as well as C=A*B+D operations in which D-summation-matrix (DSM) represents the result of a previous multiplication operation or another previously defined matrix. The RMM provides for additional CPM LOAD/STORE paths allowing overlapping of compute/data transfer operations and provides for CPM data feedback to the AMM or BMM operand inputs from a previously calculated CPM result. The RMM anticipates the use of 8, 16, and 32-bit operand reconfigurable matrix datum in conjunction with a typical external memory bus data width of 512 bits and an instruction control unit (ICU) implemented using a series of RMM configuration words (RCW) and streaming opcode functions (SOF).

Reconfigurable matrix multiplier system and method

An outer product multiplier (GPM) system/method that integrates compute gating and input/output circular column rotation functions to balance time spent in compute and data transfer operations while limiting overall dynamic power dissipation is disclosed. Matrix compute gating (MCG) based on a computation decision matrix (CDM) limits the number of computations required on a per cycle basis to reduce overall matrix compute cycle power dissipation. A circular column rotation vector (CRV) automates input/output data formatting to reduce the number of data transfer operations required to achieve a given matrix computation result. Matrix function operators (MFO) utilizing these features are disclosed and include: matrix-matrix multiplication; matrix-matrix and vector-vector point-wise multiplication, addition, and assignment; matrix-vector multiplication; vector-vector inner product; matrix transpose; matrix row permute; and vector-column permute.

Outer product multipler system and method

Embodiments are generally directed to a multithreaded processor for executing a plurality of threads, as well as an associated method and system. The multithreaded processor comprises a first control register configured to store a stack limit value, and instruction decode logic configured to, upon receiving a procedure entry instruction for a stack associated with a first thread, determine whether to throw a stack limit exception based on the stack limit value and a first predefined stack region size associated with the stack.

Reduced stack usage in a multithreaded processor

In one embodiment, command message generation and execution using a machine code-instruction is performed. One embodiment includes a particular machine executing a single machine-code instruction including a reference into a command-message-building data structure stored in memory. This executing the single machine-code instruction includes generating a command message and initiating communication of the command message to a hardware accelerator, including copying command information from the command-message-building data structure based on the reference into the command message. The hardware accelerator receives and executes the command message. In one embodiment, the command message is message-switched from a processor to a hardware accelerator, such as, but not limited to, a memory controller, a table lookup unit, or a prefix lookup unit. In one embodiment, a plurality of threads share the command-message-building data structure. In one embodiment, a plurality of processors share the command-message-building data structure.

Command message generation and execution using a machine code-instruction

A page table is a data structure used by a virtual memory system in a computer system to store the mapping between virtual addresses and physical addresses. Embodiments herein use a tree to map a virtual memory address space in the page table. The tree may be an N-ary tree where N is a power of two (e.g., 2, 4, 8, 16, etc.). The tree may include multiple levels that each correspond to a different page table size. For example, an octree includes eight different entries for each child node which may include per-thread sub-entries. Child nodes in the first level of the octree may each correspond to a 512 GiB page, while child nodes in the second level, however, may each have eight entries that correspond to a 64 GiB page. In this manner, an N-ary tree may be used to support a computing system with varying page sizes.

N-ary tree for mapping a virtual memory space

Cache lines of a data cache may be assigned to a specific page type or color. In addition, the computing system may monitor when a cache line assigned to the specific page color is allocated in the cache. As each cache line assigned to a particular page color is allocated, the computing system may compare a respective index associated with each of the cache lines to determine maximum and minimum indices for that page color. These indices define a block of the cache that stores the data assigned to the page color. Thus, when the data of a page color is evicted from the cache, instead of searching the entire cache to locate the cache lines, the computing system uses the maximum and minimum indices as upper and lower bounds to reduce the portion of the cache that is searched.

Bounded cache searches

In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.

Rule-based virtual address translation for accessing data

A system and method includes modules for determining whether an instruction is a target of a non-sequential fetch operation with an expected numerical property value, and avoiding execution of the instruction if it is the target of the non-sequential fetch operation and does not have the expected numerical property. Other embodiments include encoding an instruction with a functionality that is a target of a non-sequential fetch operation with an expected numerical property value. Instructions with the same functionality that are not targets of non-sequential fetch operations can be encoded with a different numerical property value. More specific embodiments can include a numerical property of parity, determining whether the instruction is valid, and throwing an exception, setting status bits, sending an interrupt to a control processor, and a combination thereof to avoid execution.

System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions

The present invention provides a network multithreaded processor, such as a network processor, including a thread interleaver that implements fine-grained thread decisions to avoid underutilization of instruction execution resources in spite of large communication latencies. In an upper pipeline, an instruction unit determines an-instruction fetch sequence responsive to an instruction queue depth on a per thread basis. In a lower pipeline, a thread interleaver determines a thread interleave sequence responsive to thread conditions including thread latency conditions. The thread interleaver selects threads using a two-level round robin arbitration. Thread latency signals are active responsive to thread latencies such as thread stalls, cache misses, and interlocks. During the subsequent one or more clock cycles, the thread is ineligible for arbitration. In one embodiment, other thread conditions affect selection decisions such as local priority, global stalls, and late stalls.

Thread interleaving in a multithreaded embedded processor

Multiple pipelined Translation Look-aside Buffer (TLB) units are configured to compare a translation address with associated TLB entries. The TLB units operated in serial order comparing the translation address with associated TLB entries until an identified one of the TLB units produces a hit. The TLB units following the TLB unit producing the hit might be disabled.

Translation look-aside buffer with variable page sizes

A processing engine includes descriptor transfer logic that receives descriptors generated by a software controlled general purpose processing element. The descriptor transfer logic manages transactions that send the descriptors to resources for execution and receive responses back from the resources in response to the sent descriptors. The descriptor transfer logic can manage the allocation and operation of buffers and registers that initiate the transaction, track the status of the transaction, and receive the responses back from the resources all on behalf of the general purpose processing element.

Descriptor transfer logic

A resource interconnect architecture and associated descriptor protocol provides more efficient communication between different resources in a data processing system. One embodiment uses a backdoor interconnect that allows some resources to communicate without using a central resource interconnect. Another embodiment uses nested descriptors that allow operations by different resources to be chained together without having to communicate back to an originating descriptor resource. In another embodiment, the descriptors are generated in hardware or in software. Other embodiments assign priority or privilege values to the descriptors that optimize processing and error handling performance.

Method and apparatus for communicating over a resource interconnect

Growing community of inventors

Richardson, TX, United States of America

Donald Edward Steiss