International Business Machines Corporation

Lockheed Martin Corporation

Donald E Wallis

Charles A Dennis

William W Sproul, Iii

Hubert A Miller

Michael J Buehler

Michael A Sweeney

Sidney F Rudolph

Galen Plunkett, Jr

Gary L Kratz

Eugene T Walendziewicz

Kathleen F Bonaffini

Andrew M Bonaffini

A high performance, real-time control sequencer is disclosed which incorporates a unique state matrix logic. This real-time control sequencer performs rapid resolution of control processed state transitions and the required control actions as a function of detected external events and the current control process state. The control sequencer's micro-instructions present event and current state data as inputs to a state matrix logic and initiate state matrix operations. The state matrix, in turn, outputs data defining and initiating the next control process state, required process control actions to be performed by the control sequencer microcode, process status, and event response or control output data. The real-time, event-driven data processor invention provides greater flexibility for reconfiguring event patterns to be detected and responses desired. It provides for a faster resolution of control process state transitions and the required control actions, and it accomplishes this with a larger repertoire of event patterns and responses stored in a smaller memory area, than has been required in the prior art.

Real-time control sequencer with state matrix logic

Distributed control architecture for a multiprocessor system includes a control processor operating on system programming instructions for executing system supervisory and task management functions, and a control bus over which it outputs execute instruction words containing a pointer address. Program storage stores threaded link lists of intermediate level instruction words, each list head being pointed to by the pointer address of respective execute instruction words. A first subunit processor for executing a first type function has a control input connected to a first distributed control interface processor and includes first post and wait logic for posting a signal indicating completion of a first type function. The first distributed control interface processor has a control input connected to the control bus for receiving the execute instruction word and a data input connected to program storage for accessing intermediate instruction words from a link list pointed to by the pointer address in the execute instruction word, and includes stored control programs to execute first type functions, each accessed by a respective intermediate instruction word. Each control program includes control words sequentially output to the first subunit processor. A second subunit processor controlled by a second distributed control interface processor executes a second type function in a manner similar to the first subunit processor, and includes second post and wait logic for posting a signal to the first subunit processor's post and wait logic indicating completion of a second type function, and a corresponding operation is performed by the first subunit processor's post and wait logic to coordinate execution of mutually dependent first and second type subunit functions. Thus, the control processor can initiate tasks to be performed by the first and second subunit processors and then be free to execute system supervisory and task management functions while the first and second type subunit functions are performed under control of the first and second distributed control interface processors.

Distributed control architecture with post and wait logic

A signal analyzer system is disclosed which includes an arithmetic processor containing a plurality of pipeline processor elements in parallel array with each element connected to a respective working store, with all of the elements being under microprogram control of an arithmetic element controller. A storage controller included in the system is connected to the arithmetic processor, to a system input and to a system ouput. A bulk storage included in the system is connected to the storage controller. The storage controller controls data transfers into and out of the system and between the bulk storage and arithmetic processor. A control processor included in the system is connected to the arithmetic processor and the storage controller by means of a data bus for centrally controlling the operation of the plurality of pipeline processor elements by transmitting micro control words over the bus.

Signal analyzer system

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Marblehead, MA, United States of America

Donald E Wallis