Crest Semiconductors, Inc.

Slicex, Inc.

Siflare, Inc.

Donald E Lewis

Rex K Hales

Yusuf Haque

Ryan James Kier

Paul Talmage Watkins

Ramesh Kumar Singh

A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.

Randomized time-interleaved sample-and-hold system

A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.

Time interleaving analog-to-digital converter

A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.

Time-interleaved sample-and-hold

A pipelined Analog-to-Digital Converter (ADC) includes circuitry to characterize capacitors associated with a Multiplying-Digital-to-Analog Converter (MDAC) of a stage of said pipelined ADC, said capacitors contributing to a gain of said pipelined ADC, circuitry to connect a subset of said capacitors not currently being characterized to reference signals of said pipelined ADC such that a residue signal of said stage stays within an input range of an instrument measuring said residue signal, circuitry to calculate said gain of said pipelined ADC using said capacitor characterizations, and an output adjusting component to digitally change an output of said pipelined ADC to compensate for said calculated gain.

Gain calibration

This method increases accuracy of a pipelined analog-to-digital converter comprising a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The method includes calibrating each the ADC starting from a least significant stage until all ADCs have been calibrated using a reference digital-to-analog converter, the reference digital-to-analog converter selectively outputting values at desired trip points for each the ADC; measuring an output of each the DAC using downstream stages of the pipelined analog-to-digital converter to produce output measurements; and using the output measurements to calculate an error-corrected output of the pipelined analog-to-digital converter. The trip points are adjusted by modifying a reference current input to a comparator of each the ADC.

Methods and systems for calibrating a pipelined analog-to-digital converter

A pipelined analog-to-digital converter includes a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). A method for increasing the accuracy of the pipelined ADC includes calibrating the ADC in each stage of the analog-to-digital converter by adjusting trip points of that ADC. Another method for increasing the accuracy of a pipelined ADC includes measuring error in an output of each the DAC; and correcting an output of the pipelined analog-to-digital converter for the measured error. These methods can be used together to further increase the accuracy of the pipelined ADC. Consequently, a pipelined analog-to-digital converter may include a look-up table containing data for correcting errors in output of each of the DACs, where trip points of the ADCs the ADCs in the stages of the pipelined converter have been calibrated to expected values.

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Nevada City, CA, United States of America

Donald E Lewis