Unisys Corporation

Donald E Harding

Gregory B Wiedenman

Paul A Laberge

A circuit employing two delayed bus clock signals and timer logic to minimize the dead bus time occurring between consecutive bus drivers and providing additional protection against multiple, simultaneous bus drivers for a communications bus in a computer system. Skewed enable and disable clock signals based on an original bus clock feed combinational logic to set a transceiver enable line when control of the bus is granted for bus transfers. Bus transfers remain enabled, through use of a feedback path, as long as a bus grant signal is active. When the last cycle of the bus transfer occurs, or a bus transfer error occurs, the transceiver enable line goes inactive, thereby allowing other components coupled to the bus to gain control. Test mode and bus transfer status lines provide further mechanisms for controlling bus transfer operation.

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Downingtown, PA, United States of America

Donald E Harding