International Business Machines Corporation

Donald E Carmon

Malcolm Scott Ware

William G Crouse

Llewellyn Bradley Marshall, Iv

Fetchi Chen

Jose A Eduartez

Raymond W Weeks

Charles R Knox

Gary G Allran

Frank Edward Grieco

Llewellyn B Marshall

Nathan A Mitchell

Michael Terrell Vanover

Yoav Medan

Uzi Shvadron

William W Lawton

John Joseph Bergkvist, Jr

Charles Robert Young

William L Lawton

Malcolm C Ware

An apparatus and method are implemented to track and manage system cycles stolen from a data processor by other processors in a multiprocessor data processor system. The apparatus and method maximize data throughput and minimize unused cycle resources within the multiprocessor data processing system.

Apparatus for pacing cycle steals from a data processor and methods for implementing the same

Hard, real-time, multi-tasking system is monitored by combined hardware and software and logic to detect overrun of any task beyond a declared maximum processor cycle limit for the task. Processor execution cycles utilized by DMA or interrupt processing and not related to the task being executed are not counted. Counter hardware and control logic reduces software overhead for monitoring execution cycle utilization by a task and provides capability not only of overrun detection, but programmed cycle usage alarm, consumed cycle count and overall processor loading or utilization measurements to be made.

Monitoring processor execution cycles to prevent task overrun in

System for counting clock cycles stolen from a data processor and

A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

System for controlling task execution in a host processor based upon the

System for handling requests for DMA data transfers between a host

An operating system for scheduling execution of a random set of periodically recurring hard, real-time tasks encountered in multi-media computer system applications and which is useful in a multi-tasking computer operating environment. Periodically recurring computer tasks having relatively short execution periods for which execution results are absolutely required in hard, real-time environments such as multi-media systems, create a significant task scheduling overhead reducing the available processor resource. Overhead processing at task invocation is eliminated in the invention by placing all active recurrent tasks in an execution queue, regardless of the task's current state of activity and by reprioritizing the order of execution of the tasks in the queue whenever a given task execution is completed. Measured by reduction in task scheduling overhead consumed by the processor in scheduling the tasks, this achieves a 50-100% improvement over conventional scheduling and operating systems.

Multi-media computer operating system and method

A data processing system for executing multimedia applications which interface with multimedia devices that consume or produce at least one of real-time and asynchronous streamed data includes a CPU for execution of one or more multimedia applications and a DSP for processing data including streamed data. A plurality of modular multimedia software tasks may be called by the multimedia application for execution in the DSP. A plurality of data communication modules are provided for linking selected ones of the software tasks with selected others of the software tasks, and linking selected multimedia devices with selected ones of the software tasks. Each of the communications modules allows continuous, real-time and unidirectional communication of streamed data. The modularity of the processing system defines an open architecture for real-time processing which allows additional modular multimedia tasks to be added to the software tasks and selectively linked to at least one of (a) selected ones of the software tasks, and (b) selected ones of the multimedia devices. A DSP manager is resident in the CPU which dynamically monitors resource allocation to allow at least one software task to be loaded and executed while at least one other software task is being executed by the DSP without interference with execution.

Method and apparatus for facilitating real-time and asynchronous loading

A data processing system is provided for executing multimedia applications which interface with multimedia end devices that consume or produce at least one of (a) real-time and (b) asynchronous streamed data. The data processing system includes a central processing unit for data processing operations including execution of the multimedia application, a digital signal processor for processing data including the streamed data, and a plurality of modular components which cooperate to provide a substantially open architecture. The plurality of modular components include a plurality of modular multimedia software tasks which are executable by the digital signal processor and which may be called by the multimedia application for execution in the digital signal processor, as well as a plurality of data communication modules for linking selected ones of the plurality of modular multimedia software tasks with selected others of the plurality of modular multimedia software tasks, and for linking selected multimedia end devices with selected ones of the plurality of modular multimedia software tasks. Each of the plurality of data communication modules allows continuous, real-time and unidirectional communication of streamed data. The enhanced connectivity of the modular approach for the multimedia data processing system allows additional modular multimedia software tasks to be added to the plurality of modular multimedia software tasks and selectively linked to selected ones of the plurality of modular multimedia software tasks and selected ones of the multimedia end devices.

System for facilitating continuous, real-time, unidirectional, and

A system for providing a time-based interrupt signal to a processor for executing a real time interrupt event with reduced interrupt latency, involves: a first programmable counter, which is capable of interrupting the processor by generating an interrupt signal on a regular time period based on the decrementing of an initial count value loaded therein, which value is re-loaded in the counter when the count is exhausted and the interrupt signal is generated; one or more second programmable counters, also having initial count values loaded therein that are decremented, and each of which, if the count is exhausted before that of the first counter, will not allow certain types of instructions or events, respectively associated with each second counter, to execute, if the execution of such instructions or events would cause an unwanted latency in the interrupt caused by the interrupt signal from the first counter.

System to reduce latency for real time interrupts

System for constructing a partitioned queue of DMA data transfer

A method and apparatus for controlling the readout rate of information from a sequential storage medium, such as a CD-ROM, to maintain synchronism between the device containing the medium and an independent receiver receiving the information. Information is loaded from the media into a buffer at a rate controlled by pulses from a device clock. Information is unloaded from the buffer for utilization by the receiver independently of the loading of the buffer. The amount of free space available in the buffer is measured as information is loaded into the buffer. The rate of the clock is dynamically adjusted in response to the amount of free buffer space to maintain the full state of the buffer within predetermined limits. In this manner, the buffer never empties or fills in response to the unloading by the independent receiver.

Method and apparatus for synchronizing the readout of a sequential media

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Durham, NC, United States of America

Donald E Carmon