Honeywell International Inc.

Donald Debear

Shyama P Mukherjee

Joseph A Levert

The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer tending to dwell in regions of lower surface topography, protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer. In some embodiments of the present invention, the viscous overlayer may be added prior to the introduction of etchant to the wafer surface, or both etchant and viscous overlayer may be introduced substantially simultaneously, typically as the wafer is spun during planarization.

Viscous protective overlayers for planarization of integrated circuits

An electronic component contemplated comprises a) a substrate layer, b) a dielectric layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer coupled to the conductive layer. The electronic component contemplated herein can be produced by a) providing a substrate; b) coupling a dielectric layer to the substrate; c) coupling a barrier layer to the dielectric layer; d) coupling a conductive layer to the barrier layer; and e) coupling a protective layer to the conductive layer. The protective layer may then be cured to a desirable hardness. A method of planarizing a conductive surface of an electronic component may comprise a) introducing or coupling a protective layer onto a conductive layer; b) dispersing the protective layer across the conductive layer; c) curing the protective layer; d) introducing an etching solution onto the conductive layer; and e) etching the conductive surface to substantial planarity.

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San Jose, CA, United States of America

Donald Debear