Texas Instruments Corporation

Donald Cook Richardson

Richard K Hester

Christopher Lee Betty

James Robert Hochschild

Patrick Peter Siniscalchi

Weibiao Zhang

Feng Chen

Daramana G Gata

Glenn H Westphal

Joseph T Nabicht

Subahashish Mukherjee

Kazi I Islam

A circuit and method for reducing the variation of a reference voltage as a function of resistivity &#x3c1; in a current-mode bandgap reference circuit generating a reference current that is applied to an output resistor to generate the reference voltage. According to the invention, a substantially constant current is generated and added to the reference current.

Current-mode bandgap reference voltage variation compensation

A system for providing a threshold voltage (V) includes a Vextractor that extracts the Vfor a MOS transistor relative to a first voltage rail. An inversion circuit inverts the extracted V(e.g., V+V) relative to a reference voltage that is intermediate the first voltage rail and a second voltage rail and provides an output corresponding to the V(e.g., V+V) relative to the second voltage rail. The relative voltages at the voltage rails generally will depend on whether the Vis being extracted for a p-channel MOS transistor or an n-channel MOS transistor. The Vcan be employed to generate a ramp voltage across a capacitor formed of another MOS transistor.

Threshold voltage extraction for producing a ramp signal with reduced process sensitivity

A method and apparatus in a DC-feed controller for controlling a subscriber line interface circuit controlling voltage (alternately, current) on a telephone line comprising a pair of wires. A digital feedback signal is subtracted from a predetermined voltage (alternately, current) limit digital value to provide a digital error signal that represents the difference between the voltage (alternately, current) limit digital value and the digital feedback signal. The digital error signal is multiplied by a predetermined digital gain value to provide a scaled digital error value. The scaled digital error value is integrated over time to generate an integrated digital error signal having a first predetermined number n of significant bits. A modified digital error signal is received, comprising a second predetermined number m of bits, where m&#x3c;n, of the integrated digital error signal as an input and an output an analog error signal is provided that is representative of the modified digital error signal and that comprises the control voltage. A sense signal is received, the sense signal representing a sensed voltage (alternately, current) on the telephone line, and is converted to a digital sense signal that is a representation of the sense signal. Finally, the digital sense signal is digitally low pass filtered to provide the digital feedback signal.

Hybrid DC-feed controller for a subscriber line interface circuit

The asymmetric digital subscriber line receive channel includes: first and second external resistorsandcoupled to a telephone lineand; a coarse programmable gain amplifier CPGA formed in a low voltage process having inputs coupled to the first and second external resistorsand; and a fine programmable gain amplifier PGAcoupled to an output of the coarse programmable gain amplifier CPGA, and having a very fine gain trim adjustment to compensate for a mismatch between the external resistorsandand the coarse programmable gain amplifier CPGA.

ADSL front-end in a low voltage process that accommodates large line voltages

A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a buffer having substantially unity gain with proper DC shift to drive an isolated bulk terminal of the MOS well to improve the spurious free dynamic range (SFDR). In this way, the 2nd-order effect such as nonlinear body effect (V(V)) and nonlinear junction capacitance (C(V)) can be substantially removed.

Method and structure for improving the linearity of MOS switches

The present invention accepts timing and clock signals with a desired frequency and undesired duty cycle CLKIN, and outputs a clock signal CLKOUT with the desired frequency and desired duty cycle. If the clock signal is known to have a duty cycle of greater than 50%, one exemplary embodiment of the present invention delays the rising edge of the clock signal so as to produce a clock signal with a 50% duty cycle. One exemplary embodiment of the present invention comprises a charge pump integrator () configured in a feedback loop, the output of the charge pump integrator () operable as a controlling node to delay inverter (). If the clock signal CLKIN at the input of the circuit has a duty cycle of greater than 50%, then the charge pump integrator () will, through PBIAS, cause delay inverterto delay of the rising edge of CLKIN through delay inverter (). The charge pump integrator, through PBIAS, drives the duty cycle of the clock signal towards 50%.

Circuit for modifying a clock signal to achieve a predetermined duty cycle

Digital subscriber modems ( ) for use in Asynchronous Digital Subscriber Line (ADSL) communications are disclosed. The central office modem ( ) includes a digital transceiver function ( ) and an analog front end function ( ), where the analog front end function ( ) is integrated into a single integrated circuit. According to the disclosed embodiments, the analog front end function ( ) includes a transmit and a receive side. On the receive side, an impedance matching circuit ( ) is coupled to the input of a programmable gain amplifier ( C). The impedance matching circuit ( ) is controlled by the same control signals (C , C , C ) as used to select the gain of the programmable gain amplifier ( C), so that a constant input impedance is presented to the signal input (RXP), independent of the selected gain.

Impedance matching for programmable gain amplifiers

A circuit and method is provided that allows for communication of digital to analog data over more that one channel employing a single current switching DAC and a current switching multiplexer. The current switching multiplexer is an output stage circuit that is used to steer the current from one output channel to another. The data rate of the data transmitted to the DAC is increased by the number of channels that the data is being transmitted over. The data is then switched from one channel to the other by employing a current switching multiplexer, such that the device provides for the same functionality that conventional devices utilizing a single DAC for multiple channels as opposed to a single DAC for a single channel.

Differential current multiplexer for current switched DACs

A pipelined analog-to-digital converter includes a first stage 700 of an analog-to-digital converter having a first resolution. The first stage 700 includes a three capacitor switched capacitor circuit. The analog-to-digital converter further includes one or more subsequent analog-to-digital converter stages 200. The first and subsequent stages 700 and 200 are pipelined together to provide a digital output signal.

Pipelined analog-to-digital converter

A pulse-density modulator (10) for producing a pulse density output signal on an output line (36) representing successive parallel digital input words on input terminals (12) has a plurality of full adders (14, 16, 18), each having a carry output (C), and an input (A) for receiving a respective bit of a concurrently applied bit of the parallel input digital words. The overflow output (C) of each of the adders (14, 16, 18) is added as an input (B) of an adder of a next successively higher bit order. A latch (30) receives the carry output (C) of one of the adders (14) in a most significant bit position, with an output of the latch provides a pulse density modulated signal on an output line (36) representing the input digital words. A clock (35) applies clock pulses to the latches (20, 22, 24, 30) at a frequency at least as high as the frequency at which the successive parallel digital input words are applied to the inputs (12) of the adders (14, 16, 18).

Digital integrator for pulse-density modulation using an adder carry or

A method and apparatus for correcting errors in a thermometer code data array (32). A parallel A/D converter (22) comprises an array (26) of comparators and an encoder (30). The correction of errors in the data array (32) produced by the comparators (26) is accomplished by an array (24) of majority error correction gates which is placed between the array (26) of comparators and the encoder (30) in the A/D converter (22).

Method and apparatus for error correction in thermometer code arrays

An integrated circuit automatic gain control circuit maintains an alternating input signal at a predetermined amplitude. A ladder network of capacitors and accompanying FET switches provides for varying the gain of an integrated switched capacitor filter. The output signal from the filter is compared in a comparison circuit, the comparison circuit providing an UP signal if the output signal is too small or a DOWN signal if the output signal is too large. The UP and DOWN signal is applied to a ROM which causes a counter to count up or down in response to the UP or DOWN input signal, the counter inputting the ROM to provide control signals from the ROM for controlling the switches of the capacitor ladder network.

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Plano, TX, United States of America

Donald Cook Richardson