Texas Instruments Corporation

Donald Charles Abbott

Douglas W Romm

Raymond A Frechette

Paul R Moehle

Robert M Fritzsche

Bernardo Gallegos

David W West

Michael E Mitchell

Gregory Eric Howard

Siva Prakash Gurrum

Darvin R Edwards

Rajiv Carl Dunne

Howard Raeburn Test

Manu Joseph Prakuzhy

Marco Corsi

Taylor R Efland

Louis N Hutter

Chi-Cheong Shen

John P Erdeljac

Charles E Williams

Konrad Wagensohner

Quang X Mai

Edgar Rolando Zuniga-Ortiz

Usman Mahmood Chaudhry

Walter Bucksch

Kathryn Ann Schuck

Christopher M Sullivan

Robert A Sabo

Masood Murtuza

Satyendra Singh Chauhan

Margaret Simmons-Matthews

Milton Lee Buschbom

Mohendra S Bawa

Ubol Udompanyavit

Steve Smith

Bawa S Mohendra

George A Dainis, Iii

John E Cotugno

Brian Eugene Parks

In described examples, a method for electroplating a semiconductor device includes: forming a metal foil; forming an inert anode support; attaching the metal foil to the inert anode support to form an anode; forming a cathode using a semiconductor substrate; immersing the anode and the cathode within an electrolyte solution; forming a circuit with a current source, the anode and the cathode; generating a current through the circuit; and electroplating a metal from the electrolyte solution onto the semiconductor substrate.

Method and system for electroplating a MEMS device

In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.

Selective planishing method for making a semiconductor device

A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.

Semiconductor package having etched foil capacitor integrated into leadframe

A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.

A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed. Sidewalls of the first metal are coplanar with the foil sidewalls. The second mask is removed.

A semiconductor device () includes a leadframe having a chip pad () and a lead () with a first end () proximate to the pad and a second end () remote from the pad, the leadframe having a base metal () including copper and a stack of a plated first layer () of nickel in contact with the base metal and a plated second layer () of a noble metal in contact with the nickel layer, the second lead end free of the noble metal. Further included is a copper wire () having a ball bond () on a semiconductor chip () attached to the chip pad, and a stitch bond () on the proximate lead end, the stitch bond penetrating the second layer; furthermore a packaging compound () encapsulating the chip, the wire, and the first end of the lead, the compound leaving the second end of the lead un-encapsulated; and the unencapsulated second lead end covered with a plated third layer () of solder.

Copper leadframe finish for copper wire bonding

A method for fabricating a leadframe strip is disclosed. A leadframe pattern is formed from flat sheet of base metal. Additional metal layers are plated on patterned tape of base metal and the leadframe surface is roughed. A first set of leadframe areas is planished. A second set of leadframe areas are offsetted and the tape is cut into strips.

Selective leadframe planishing

A semiconductor device includes a leadframe, a semiconductor chip, a packaging compound. The leadframe has a pad with straps. Leads on the leadframe include first and second portions. The pad, the straps, and the leads have a mechanically rough surface. The semiconductor chip is attached to the pad and wire bonded to the first lead portions. A packaging compound encapsulates the chip, the pad, the straps, the bonding wires and the first lead portions. The second lead portions are left un-encapsulated. The strap ends are exposed on the surface of the package. At least one of the straps includes a portion adjacent to the exposed end. This portion having a mechanically smooth surface transitioning by a step into the rough surface of the remainder of the strap.

Semiconductor device with selective planished leadframe

An integrated circuit package may be formed using a leadframe having an open space extending therethrough. A shunt is located within the open space such that it is not in contact with any portion of the leadframe. Tape may be applied to the lower surface of the leadframe to support the shunt and hold it in place relative to the leadframe until wirebonding and encapsulation have been completed. Thereafter, the tape may be removed.

Method of manufacture integrated circuit package

A metal leadframe strip () for semiconductor devices is described. The leadframe strip has a plurality of sites () for assembling semiconductor chips. The sites alternate with zones () for connecting the leadframe to molding compound runners. The sites () have mechanically rough and optically matte surfaces (). The zones () have at least portions with mechanically flattened and optically shiny metal surfaces (). The flattened surface portions transition into the rough surface portions by a step.

Leadframe having selective planishing

Strip testing is applied to a plurality of integrated circuit dies that are each encapsulated in an encapsulant, that each have a set of externally accessible leads connected thereto, and that are electrically isolated from one another. Provision is made for the strip testing to be performed without mounting the encapsulated integrated circuit dies on a support tape.

Singulation and strip testing of no-lead integrated circuit packages without tape frame

In a method and apparatus for fabricating a semiconductor device having a flexible tape substrate, a hole is punched in the flexible tape substrate. The flexible tape substrate includes a metal layer attached to a polyimide layer without an adhesive there between. A cover is placed on the metal layer to cap a base of the hole. A metal is deposited on the cover exposed at the base of the hole, the metal being used to form a bond with the metal layer. The metal being deposited causes the hole to be plugged up to a selective height. Upon removal of the cover, the metal may also be deposited on the metal layer to increase a thickness of the metal layer.

Metal plugged substrates with no adhesive between metal and polyimide

A semiconductor device without cantilevered leads uses conductive wires () to connect the chip terminals to the leads (), and a package compound () to encapsulate the chip surface () with the terminals, the wires, and the lead surfaces with the attached wires. The chip surface () opposite the terminals together with portions () of the chip sidewalls protrude from the package, allowing an unimpeded thermal contact of the protruding chip surface to a substrate () to optimize the thermal flux from the chip to the substrate. Solder bodies () attached to the compound-free lead surfaces () can be connected to the substrate so that the solder bodies are as elongated as the protruding chip height, facilitating the void-free distribution of an underfill compound into the space between chip and substrate, and improving the absorption of thermomechanical stresses during device operation.

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Norton, MA, United States of America

Donald Charles Abbott