International Business Machines Corporation

Donald C Wheeler

Rebecca D Mih

Jack Allan Mandelman

Louis L Hsu

Jeffrey P Gambino

Timothy A Brunner

Eric Peter Solecky

Charles Neill Archie

Mark E Lagus

Diana Nyyssonen, Deceased

By Jeffrey Swing, Legal Representative

A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall while simultaneously removing the polysilicon on the first sidewall. The polysilicon spacer forms a floating gate which is surrounded on a plurality of sides by the second sidewall.

Flash memory structure using sidewall floating gate

A wafer metrology structure for measuring both critical dimension features of multiple patterns of a semiconductor device and overlay measurements of one pattern with respect to another. The measurements are readable by a single, one-dimensional scan of a metrology system. The wafer metrology structure includes at least a first feature of a first dimension formed in a first level of the semiconductor device. The first dimension is identical to a first critical dimension of a pattern formed in the corresponding first level. A wafer metrology pattern according to the present invention also includes a second pattern of a second dimension formed in a second level of the semiconductor device. The second pattern includes an aperture superposed over the first feature. The aperture exposes at least the first feature having a critical dimension of the first pattern and thus enables a metrology system to directly measure the first feature through the aperture. The second pattern also includes a feature having a second dimension identical to a second critical dimension of the second pattern formed in the corresponding second level.

Wafer metrology structure

Flash memory structure using sidewall floating gate and method for forming the same

Selective reduction of sidewall slope on isolation edge

A photo mask and a method for using the photo mask to make asymmetric resist patterns are provided. A wafer having a resist coating thereon is exposed using the mask of the invention under specially controlled defocus conditions to provide the asymmetric resist pattern profile. The mask which comprises phase shifter means on one or both sides of a light shielding pattern forming material on the mask provides light passing through the mask having a different phase on each side of the light shielding material which produces an asymmetric resist pattern profile.

Asymmetrical resist sidewall

Disclosed is an asymmetric field effect transistor which comprises a first region serving as source, a second region serving as drain, a thin gate oxide and a gate electrode. The gate electrode is asymmetric and one of its sidewalls is sloped. The second region extends underneath said sloped sidewall. The part of said second region which extends underneath said gate electrode is less doped than the remaining part of said second region. Furthermore, said second region has a sloped junction edge underneath said gate electrode.

Asymmetrical field effect transistor

A photomask and a method for using the photomask to make dimensionally controlled resist patterns are provided. A wafer having a resist coating thereon is exposed using the mask of the invention under specially controlled defocus conditions to provide the dimensionally controlled resist pattern profile. The mask which comprises multiple phase shifter means on one side of at least one of the light shielding patterns on the mask provides light passing through the mask having multiple phases on that side of the light shielding material which produces a dimensionally controlled resist pattern profile.

Multi-phase mask

A method for monitoring a process in which a feature is formed on a substrate. A plurality of dimensions of the feature are measured using a tool. An edge width of the feature is calculated based on the plurality of dimensions. The edge width is used to determine whether the process is operating within a desired specification. The calculated edge width is compared to a baseline edge width measurement to determine a difference between them. The process is determined to be operating within the specification if the difference is less than a threshold value. If the difference is greater than or equal to the threshold value, the method determines whether the difference is caused by a change in resolution of the tool. A plurality of diagnostic measurements of the edge width may be performed. The tool is adjusted to have a respectively different focus for each respective one of the plurality of diagnostic measurements. The method includes determining that the difference between the calculated edge width and the baseline edge width is caused by a change in resolution of the tool if any one of the plurality of diagnostic measurements of the edge width differs from the baseline edge width by less than the threshold value. The method also includes determining that the process is not operating within the specification, if the difference is greater than or equal to the threshold value, and the difference is not caused by a change in resolution of the tool.

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Beacon, NY, United States of America

Donald C Wheeler