Rambus Inc.

Google Inc.

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Kabushiki Kaisha Toshiba

Xilinx, Inc.

Netlogic Microsystems, Inc

Intel Corporation

Leland Stanford Junior University

Donald C Stark

Craig Edward Hampel

Frederick Abbott Ware

Richard Maurice Barth

Ely K Tsern

Kevin S Donnelly

Bruno Werner Garlepp

Paul G Davis

Jun Y Kim

Mark A Horowitz

Stefanos Sidiropoulos

Abhijit Mukun Abhyankar

Leung Yu

Matthew Murdy Griffin

David Nguyen

Roxanne T Vu

Jared L Zerbe

Pak Shing Chau

James A Gasbarro

John Bradly Dillon

Tsyr-Chyang Ho

Benedict Chung-Kwong Lau

Jason Rupert Redgrave

Richard E Perego

Albert Meixner

Ofer Shacham

Daniel Finchelstein

Qiuling Zhu

Natsuki Kushiyama

David Patterson

Clemenz L Portmann

Benedict C Lau

Michael Tak-Kei Ching

Kurt T Knorpp

Thomas H Lee

Mark G Johnson

Chanh Vi Tran

Yiu-Fai Chan

Andrew V Anderson

Wayne S Richardson

Nhat M Nguyen

Thomas J Holman

William R Mark

Clemenz Lenard Portmann

Neeti Desai

Steven Cameron Woo

Peter D MacWilliams

Lawrence Lai

Dean Liu

Tohru Furuyama

Billy Wayne Garrett, Jr

Edward Y Chang

Thomas J Sheffler

Catherine Yuhjung Chen

Nancy David Dillon, Legal Representative

Timothy Chang

Abhijit Mukund Abhyankar

Shigeo Ohshima

Satoru Takase

Warren E Cory

Paul Kingsley Rodman

Kiyofumi Sakurai

Shahriar Rabii

Hiroyuki Noji

James Alden Weaver

Prasun K Raha

Edward T Chang

Nancy David Dillon

By Nancy David Dillon

James A Gasborro

Jessica E Melin

James A Gasbarre

Daniel Frederic Finchelstein

Kevin S Donelly

Jared Levan Zerbe

Horowitz Mark A A

Methods, systems, and apparatuses for defending against cryptographic attacks using clock period randomization. The methods, systems, and apparatuses are designed to make side channel attacks and fault injection attacks more difficult by using a clock with a variable period during a cryptographic operation. In an example embodiment, a clock period randomizer includes a fixed delay generator and a variable delay generator, wherein a variable delay generated by the variable delay generator is based on a random or pseudorandom value that is changed occasionally or periodically. The methods, systems, and apparatuses are useful in hardware security applications where fault injection and/or side channel attacks are of concern.

Clock period randomization for defense against cryptographic attacks

An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.

Two dimensional shift array for image processor

An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.

Architecture for high performance, power efficient, programmable image processing

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Flash memory controller with calibrated data communication

An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.

Described are memory systems in which a memory controller issues commands and addresses to multiple memory modules that collectively support each read and write transactions. A common set of control signal lines from the controller communicates the same command and address signals to the modules. For write commands, the controller sends subsets of write data to each module over a respective subset of data lines. For read commands, each module responds with a subset of the requested data over the respective subset of data lines. The memory modules can be width configurable so that a single full-width module can connect to both subsets of data lines to convey full-width data, or two half-width modules can connect one each to the subsets of data lines.

Memory systems with multiple modules supporting simultaneous access responsive to common memory commands

Memory controller that calibrates a transmit timing offset

A clock signal for use by a circuit can be switched between clocks glitchlessly. A series of delay devices are connected in series based on an integral timing ratio. The integral timing ratio can be based on a ratio of the one of the clock's frequency or period to the other's frequency or period. When a clock select signal is received, the select signal is qualified and then delayed an amount of time based on the integral timing ratio, using the delay devices. The number of delay devices in each series can be the next largest integer to the integral timing ratio, plus one. The clock signal can then be glitchlessly switched from one clock to the other.

Methods and systems for switching between clocks

Described is a printed-circuit board (PCB) that supports memory systems in which the memory core organization changes with device width. The PCB includes a memory-controller mounting location and module connectors to receive respective memory modules. Each module connector connects directly to the controller mounting location via a respective set of system data lines that does not connect to any other module connector. System data lines also extend directly between module connectors to support memory configurations with different numbers of modules. The memory systems support one memory module of a wide data width or multiple memory modules of narrower data widths. The number of physical memory banks accessed reduces with device data width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

Printed-circuit board supporting memory systems with multiple data-bus configurations

Memory system with calibrated data communication

Growing community of inventors

Los Altos, CA, United States of America

Donald C Stark