The Aerospace Corporation

Other

Donald C Mayer

Jon Victor Osborn

Siegfried W Janson

Peter D Fuqua

Kenneth P MacWilliams

Everett E King

Ronald C Lacoe

An annular segment MOSFET structure has reduced drain electric fields for a given applied voltage and dimensional sizing for improved reliability from damage by reducing high energy hot carriers laterally traversing the channel by reducing the intensity of electric fields in the MOSFET structure by creating diverging electric field lines with decreased electric field strength at the drain, while enabling compact integrated layouts of multiple MOSFETs within a square area of surface silicon.

Annular segmented MOSFET

An address element, including a polysilicon resistor functioning as a heating element and blocking diode preventing sneak current to unaddressed elements, is selectively addressed using row and column address lines in a thin film structure having a minimum number of address lines and a minimum number of layers. The resistor heater element is well suited for igniting a fuel cell such as a fuel cell in an array of fuel cells disposed in a thin film microthruster.

Addressable diode isolated thin film cell array

Addressable diode isolated thin film array

The method addresses and interrogates addressable cells having at least one element including a polysilicon resistor functioning as a heating element and blocking diode preventing sneak current to un addressed elements, for selectively addressing one of the cells using row and column address line in a thin film structure having a minimum number of address lines and a minimum number of layers. The resistor heating element can be used for igniting a respective fuel cell in an array of fuel cells disposed in a thin film microthruster. After ignition, the address lines are used to interrogate the cell location for verification of fuel cell ignition well suited for monitoring fuel burns and usage of the microthruster.

Diode isolated thin film fuel cell array addressing method

A silicon-on-insulator (SOI) gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor (MOSFET) includes a source, channel and drain surrounded by a top gate and a buried bottom gate, the latter of which also has application for other buried structures and is formed on a bottom gate dielectric which was formed on source, channel and drain semiconductor layer of an SOI wafer. After forming a planar bottom insulator layer on the bottom gate and bottom gate dielectric, the SOI wafer is flip-bonded onto an oxide layer of a bulk silicon wafer, thereby encapsulating the buried bottom gate electrode in insulating oxide, after which the SOI substrate and the etch-stop SOI oxide layer are removed to expose the SOI semiconductor layer which is processed to form the source, drain and channel in a mesa structure on which is deposited a top gate dielectric, a top gate, and top gate insulator as well as four conductors for connecting to the source, drain, top gate and bottom gate. The latter two electrodes can be independently controlled or commonly controlled for enhanced operation of GAA MOSFET having improved isolation and reduced parasitic capacitance due to the use of encapsulating insulation layers of the merged wafer consisting of the bonded SOI wafer and bulk silicon wafer.

Silicon-on-insulator gate-all-around mosfet fabrication methods

A gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor (MOSFET) includes a source, channel and drain surrounded by a top gate and a buried bottom gate, the latter of which also has application for other buried structures and is formed on a bottom gate dielectric which was formed on source, channel and drain semiconductor layer. After forming a planar bottom insulator layer on the bottom gate and bottom gate dielectric, the device is flip-bonded to an oxide layer of a bulk silicon wafer, thereby encapsulating the buried bottom gate electrode in insulating oxide. The semiconductor layer forms the source, drain and channel in a mesa structure on which is deposed a top gate dielectric, a top gate, and top gate insulator as well as four conductors for connecting to the source, drain, top gate and bottom gate. The latter two electrodes can be independently controlled or commonly controlled for enhanced operation of GAA MOSFET having improved isolation and reduced parasitic capacitance due to the use of encapsulating insulation layers of the merged wafer consisting of two bonded wafers.

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Palos Verdes Estates, CA, United States of America

Donald C Mayer