Tektronix, Inc.

Tut Systems, Inc.

Nexus Technology, Inc.

Donald C Kirkpatrick

Samuel J Peters, Ii

David A Holaday

David D Chapman

Gary K Richmond

Craig L Overhage

Claude Denton

Tim E Sauerwein

Apparatus and methods for generating checksums may process two or more segments of a message in parallel, and may be used with a communications channel having time slots. An apparatus may include a cumulative checksum generator to generate a cumulative checksum for a message, a partial checksum generator to generate one or more partial checksums from one or more respective message segments, and a speculative checksum generator to generate a speculative checksum for each of one or more time slots. In one aspect, a partial checksum corresponding with an initial segment of the message may be generated from at least an initialization vector. A speculative checksum selector may select a first speculative checksum for use in determining whether the message was transmitted without error. The generating of partial and speculative checksums results in a maximally pipe-lined architecture with speed limited only by a minimal cumulative CRC calculation that is fundamentally unavoidable.

Speed-optimized computation of cyclic redundancy check codes

A test and measurement instrument such as a Logic Analyzer, or the like, has at least one Reloadable Word Recognizer whose reference value can be loaded by a trigger machine with a current acquired data sample while data is being acquired. In a second embodiment useful for performing memory testing, the reloadable word recognizer is used in cooperation with two conventional word recognizers. In a third embodiment, a delay unit is employed to provide delayed input data words as reference words. In a fourth embodiment, an offset register and adder are used to modify the input data words before storing them. A fifth embodiment provides for substantially immediate use of base addresses of relocatable subroutines and stack-based variables recovered from a data stream acquired from a system under test.

Reloadable word recognizer for logic analyzer

A method and apparatus enabling the analog and digital triggering of a signal analysis device such as a Logic Analyzer, wherein separate analog and digital signal paths provide separate analog and digital processing of an input test signal for enabling the triggering of a signal analysis device upon analog and digital signal conditions.

Method and apparatus for the digital and analog triggering of a signal analysis device

An apparatus for resynchronizing data between two modules sharing a common clock where the common clock is delayed at the second module has means for storing multiple copies of the data in the first module in a recirculating manner using a Johnson counter to cycle through storage locations. A multiplexer in the second module has the copies from the first module as inputs and selects in response to a select signal generated from the delayed version of the common clock and an enable signal from the Johnson counter synchronizing each of the copies in turn such that the copy selected has just not been written or is just not about to be written to assure that the data is in a stable state.

Data resynchronization between modules sharing a common clock

A SONET path/ATM physical layer transmit/receive processor ASIC for OC-48 makes use of a 32-bit wide interface between a source/destination and the rest of the processor. Adjacent the interface is an ATM cell processor, and between the ATM cell processor and a transmission medium is a SONET payload processor. Selectors are located between the transmission medium and the SONET payload processor, the SONET payload processor and the ATM cell processor, and the ATM cell SONET path/ATM physical layer path, an ATM physical layer path or a fast FIFO buffer path according to the configuration of the selectors determined by user commands from a command logic circuit coupled to each of the interface, ATM cell processor and the SONET payload processor.

SONET path/ATM physical layer transmit/receive processor

A logic analyzer acquires all data and clock signal inputs asynchronously at high speed using a digital FISO (10) to produce a plurality of parallel high-speed data samples within each cycle of an internal system clock (95). The plurality of parallel high-speed data samples describe the sequential behavior of one of the input signals during one period of the internal system clock. One of the plurality of parallel high-speed data samples is then selected to be the single data sample that is stored in the acquisition memory (80) for that clock cycle. The selection process includes a skew adjustment (20), clock edge detection and selection (50), aligning the sample associated with the detected and selected clock edge to a reference location (60), and selecting (70) as the single sample to be stored a sample having a relationship to the reference location that is determined by setup and hold adjustment data. The transitions detected are enabled (102) and ORed (108) to produce a setup and hold violation signal only if they are within the interval established by a set of setup and hold window mask signals.

Oversampled logic analyzer

A transaction analyzer, for use in conjunction with a data acquisition system having a probe for accessing binary data, i.e. address and control signals appearing at the terminals of an operating microprocessor, determines the type of processor transaction occurring based on sequences of state changes occurring on a selected set of the control signals so accessed. The transaction analyzer then generates a binary number representing the transaction type which may be acquired by the acquisition system in conjunction with the data accessed by the probe. The transaction analyzer, which uses an asychronous state machine, also generates control signals used by the acquisition system to clock data storage along with a signal to control the direction of flow of data signals between the processor and the acquisition system. The transaction analyzer is programmable such that it may be used with a variety of different types of microprocessors which may be accessed by the probe, even though such microprocessors may generate differing control line state change patterns during processor transactions and even though transaction types may vary from processor to processor.

Transaction analyzer

An asychronous state machine waits a variable length of time after first detecting a change in input state before initiating a machine state change, the new machine state being a function of the previous machine state and the input state at the end of the waiting time, thereby allowing multiple, non-simultaneous input changes to occur during said waiting time without initiating intermediate state changes. The waiting time is a function of the current state of the machine. One state variable of a set characterizing the current state of the machine indicates whether the current state is an interim state in a sequence of states occurring after an input state change. Following a machine state change, this sequencing state variable initiates a subsequent state change, in the absence of any further input state changes, when the sequencing state variable associated with the current machine state indicates that the current machine state is such an interim state of a sequence of states.

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Beaverton, OR, United States of America

Donald C Kirkpatrick