Honeywell Information Systems Inc.

Bull Hn Information Systems, Inc.

Other

Donald C Boothroyd

Robert W Norman, Jr

William A Shelly

Ronald E Lange

John E Wilhite

Bruce E Flocken

Howard J Keller

Russell Wayne Guenthner

Clinton B Eckard

Minoru Inoshita

Ronald W Yoder

Mark T Chase

In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, a first BPU transfers to cache storage only the even bits of a given data manipulation result, and a second BPU correspondingly transfers to cache storage only the odd bit information of the result. One BPU segregates the even bits of the result, adds parity information and sends the even bits and parity information to the cache unit. Similarly, the second BPU segregates the odd bits of the result, adds parity information and sends the odd bits and parity information to the cache unit. In the cache unit, the even and odd bit information are separately parity checked before storage into cache memory. If a parity error is observed in either set of information, an error signal is issued to institute appropriate remedial action.

Central processor with duplicate basic processing units employing

In order to validate data manipulation results in a CPU which incorporates duplicate basic processing units or integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation to obtain first and second data manipulation results, which should be identical, and a cache unit for receiving data manipulation results from both BPUs and for transferring specified information words simultaneously to both BPUs upon request. These operations are controlled by cache interface control signals identically generated in each BPU. In each BPU, the control signals are arranged into first and second groups which are nominally identical. The first control signal group is transmitted to the cache unit from one BPU while the second control group is transmitted to the cache unit from the other BPU. In each BPU, parity is generated for each control group separately. Parity for the group sent to the cache unit by each BPU is included with the control signal information for checking in the cache unit. Parity for the group not sent to the cache unit by each BPU is transmitted to the other BPU and checked against the locally generated parity for that group. In the event of a parity miscompare sensed in either BPU or a parity error sensed in the cache unit, an error signal is issued to institute appropriate remedial action.

In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information. Each cache unit includes bit-by-bit comparison circuitry to validate the half-byte results received from both BPUs in the case of single precision operations, and, in the case of double precision operation, one cache unit employs the same bit-by-bit comparison circuitry to validate, for both cache units, the result parity bits, and hence the half-byte results, received from both BPUs. In a single precision test mode of operation, test signals internal to the BPUs are issued in complementary half-bytes on the normally redundant result busses and are directed to an external logic analyzer or other test equipment for conventional analysis. In addition, when no stores are being made but the BPUs are manipulating data, the test signals may be furnished to the external test equipment in the same manner, the type of operation, single or double precision, being irrelevant.

Central processing unit using dual basic processing units and combined

In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information. Each cache unit includes bit-by-bit comparison circuitry to validate the half-byte results received from both BPUs in the case of single precision operations, and, in the case of double precision operation, one cache unit employs the same bit-by-bit comparison circuitry to validate, for both cache units, the result parity bits, and hence the half-byte results, received from both BPUs.

Apparatus for detecting differences between double precision results

Binary-Coded-Decimal to binary (DTB) and binary to Binary Coded Decimal (BTD) instructions are executed by an address and execution (AX) chip, a decimal numeric (DN) chip, and a cache. For a DTB instruction, the DN chip receives the operand to be converted from the cache, saves the sign, and stores it in a conversion register. When a bit is converted, a Ready-to-Send signal is sent on a COMFROM bus with a Ready-to-Receive Command on a COMTO bus causes the AX chip to accept the bit and the DN chip to generate the next bit until the resultant operand is produced. If the operand to be converted is negative, the DN chip inverts each remaining bit after the first '1' to obtain a two's-complement result. The result in either case is sent to the cache. For a BTD instruction, the AX chip receives the operand to be converted from the cache, send the sign bit to the DN chip and then the bits of the operand when the Ready-to-Send and Ready to Ready-to-Receive signals are produced. The resultant operand is sent to the conversion register. If the operand is negative, all bits are inverted, and a one is added to produce the resultant in two's complement notation.

Binary to binary coded decimal and binary coded decimal to binary

The present invention relates to an apparatus for providing a data available indication while inhibiting the reading of operand data beyond the last word of an operand data string. The data available indication operates to enable additional cycles to be generated for completing the execution of the instruction. The apparatus includes a memory element, which has a plurality of locations, each of the plurality of locations corresponding to a respective location of a memory device where the operand data string is stored. The memory element stores information which indicates when the corresponding location is the last word of the operand data string. A read address register which contains the read address value of the memory device includes an input strobe terminal which receives an enable signal based on the information stored in the memory element, thereby enabling or inhibiting the updating of the read address value in the read address register.

Data available indicator for an exhausted operand string

The present invention relates to the operational control of a digital computer system which includes the digital logic circuitry for temporarily storing results internal to an execution unit. An input unit of the execution, which inputs operand words to the execution logic of the execution unit, includes a first stack for holding operand words received from an external memory unit and a second stack for holding the result words of the execution logic. The input unit also includes a switch element for selecting words stored in the first and second stack which are to be utilized as input operand words to the execution logic in response to at least one control signal.

Wraparound buffer for repetitive decimal numeric operations

The present invention relates to a method within a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The method includes loading the temporary storage memory with the first and second operand data strings in a pre-established order such that the subsequent fetching of the operand data words from the temporary storage memory is performed in a sequential order. The loading and fetching steps operate to achieve a desired word order such that the operation between operand data strings can be started while the operand data is being fetched.

Method for decreasing execution time of numeric instructions

The present invention relates to an operational control of a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The present invention includes an adder for adding the current read address value to a constant thereby generating a new read address value used to read the operand data on the next cycle. A preselected constant is provided to the adder each cycle, which causes the resultant new read address value to forward or reverse read the operand data.

Apparatus for forward or reverse reading of multiple variable length

The present invention relates to an execution unit of a computing system which executes data manipulation type instructions and arithmetic type instructions on data words having a plurality of decimal character-type data formats. The pipelined execution unit of the present invention includes a first stage element which temporarily stores input data, the input data including operation commands defining said decimal type instructions, and input operand data. A second stage element executes a first predetermined group of the decimal type instructions. A third stage element, operatively coupled to said second stage element, executes a second predetermined group of the decimal type instructions, the second predetermined group including arithmetic type instructions.

Pipelined decimal character execution unit

The present invention relates to an alignment network for aligning data words having a plurality of data word formats. A plurality of shifters are utilized, each shifter utilized to shift the corresponding bit of each character. When the output data word format is different from the input data word format, selected characters in response to a predetermined control signal are temporarily stored so that they may be inputted to the shifters on the next shift cycle in order to achieve the desired shifted character order. An alignment switch then aligns or packs the shifted data from the output of the shifters to the predetermined data format in response to a select control signal.

Apparatus for aligning and packing a first operand into a second operand

The present invention relates to digital logic circuitry for detecting a predetermined character of a data string for operand data stored in a temporary storage memory or while the data is being loaded into the temporary storage memory, wherein the data string length and the starting location of temporary storage memory in which the data string is to be stored is variable. A first comparator element compares a write address pointer to a start address pointer and an adder generates a sign pointer which indicates an address of temporary storage memory of the predetermined character. A second comparator element utilizes the pointers and the resultant outputs of the first comparator and the adder to indicate the end of the data string.

Apparatus for detecting a predetermined character of a data string

The present invention relates to an alignment network for aligning data words having a plurality of data word formats. A plurality of shifters are utilized, each shifter utilized to shift the corresponding bit of each character. The odd bits, or nonsymmetrical bits across the various data formats are processed by a separate shifter. In this manner, no pre or post processing of the data word is required in the overall shifting operation.

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Phoenix, AZ, United States of America

Donald C Boothroyd