Motorola Corporation

Other

Donald C Anderson

Peter C Curtis

Chia-Shiann Weng

Walter U Kuenast

Paul M Astrachan

Keith Duy Dang

William C Moyer

Hunter Ledbetter Scales, Iii

Jose G Corleto

Mark E Burchfield

Gregg S Kodra

Kenneth C Weng

Richard L Greene

Edmund S Lee, Iii

Kenneth L McIntyre

Jeffery P Bray

An electric motor powered vehicle includes an energy reservoir provided by a battery-mass flywheel having a diameter approximately equal to the vehicle lateral wheel spacing, allowing a compact configuration. The flywheel may include a pair of counter rotating wheels mounted on concentric shafts and may be enclosed in a containment device. A shoe-rail electrical connection facilitates transfer of current to and from the batteries. The flywheel may include fuel cells charged from a remote hydrogen source. Flywheel, alternator and friction braking may be controlled by pedal movement. Energy may be transferred to the battery mass flywheel independently of vehicle motor drive. The motor-flywheel drive connections are made through inputs to a differential gear drive. The fuel cells may charge the batteries, and a second alternator may recover flywheel energy at vehicle shut-down.

Regenerative self propelled vehicles

A malodor control system for a toilet comprises a modified toilet seat which is a hollow construction. The seat may be mounted on supports for pivotal movement between an up position and down position in which its opening is registered with the opening of an toilet bowl for receiving products of human waste. As in conventional toilets, portions of a person sitting on the seat define a chamber, in combination with the seat and the bowl. A pair of water spray nozzles are disposed within the hollow seat and directed rearwardly toward the pivotal mounting for the seat. A water supply system includes a flexible tube connection between a fixed source of pressurized water and a bracket for pivotally mounting the seat. Flow of water to the spray nozzles is controlled by a valve on the rear of the seat. The water spray induces flow of fouled air from the user defined chamber into the hollow seat where offensive odors are removed by the water spray. Entrainment separators, downstream of the spray nozzles, precipitate water from the air. The water is then returned to the toilet bowl, while the clensed air is discharged from the seat. An air freshener unit, downstream of the entrainment separator further additionally treats the air to make it more pleasant.

Malodor control systems for toilets

A data processor (40) includes source (60) and destination (61) address generation units (AGUs) to update source and destination addresses for efficient digital signal processing (DSP) functions. The data processor (40) includes an instruction decoder (41) which recognizes a bit movement instruction, which is frequently encountered in data interleaving operations. In response to the bit movement instruction, the instruction decoder (41) causes the source (60) and destination (61) AGUs to update their present addresses using variable offset values. The instruction decoder (41) further causes a bus controller (44) to convert these bit addresses to corresponding operand addresses and bit fields. The bus controller (44) accesses source and destination operands using the operand addresses. The instruction decoder (41) then causes an execution unit (45) to transfer a bit from the source operand indicated by the source bit field to a bit position of the destination operand indicated by the destination bit field.

Data processor with an efficient bit move capability and method therefor

A DSP co-processor (72) that is used on an integrated circuit (24) that provides multiple communication functions is accomplished by providing a data bus interface (320), a sequencer (328), internal memory (33), and a data core (322). The sequencer (328) stores in a hardware format a signal processing algorithm (332) and, upon receipt of an operational command, provides address control signals (334) and operation control signals (336) to the data core (322). The data core (322), which includes an address generation unit (340) and an arithmetic unit (344), executes, via the arithmetic unit, operational instructions of the signal processing algorithm to produce resultant signals from the input samples, the intermediate resultants, and the algorithm co-efficients.

DSP co-processor for use on an integrated circuit that performs multiple

An integrated circuit that provides multiple communication functions is accomplished by providing an integrated circuit (24) that includes memory (70) which stores an audio code algorithm, echo cancellation information, a modem processing algorithm, and audio data. The memory (70) is coupled via a data bus (50) to a signal converter (56), a central processing unit (58), and a first co-processor (72). The signal converter (56) provides an analog-to-digital input port (78) and a digital-to-analog output port (80) for the integrated circuit (24), wherein the audio data is received via the analog-to-digital input port (78). The central processing unit (58) executes at least a first portion of the audio coding algorithm upon the audio data and executes a first portion of the modem processing algorithm, while the first co-processor (72) executes an echo cancellation algorithm.

Integrated circuit that performs multiple communication tasks

An odor control system for capturing odoriferous air from toilet bowls, removing the odor bodies from the air, and returning the cleansed air to the room. A fine water spray nozzle (32) in a duct (30) transfers kinetic energy to the air stream, and also absorbs odor bodies from the air. Energy to generate the water spray and draw air through a ventilated toilet seat is provided by the water under pressure which supplies the usual toilet function. System is started and stopped as needed by the person using the toilet. Supplemental filter (36), e.g. Activated carbon, improves odor cleansing by adsorption. Spray water used is separated from air stream and returned to toilet bowl (20) through check valve (38).

Odor control system for toilets

In a decoding apparatus (100), overflow conditions can be determined within the same clock cycle by determining the type of operation to be performed. For time sensitive operations, a load (102) and a discharge device (105) are temporarily coupled to a dynamic decoding structure (101) of the decoding apparatus (100). The load (102) and the discharge device (105) allow the decoding apparatus (100) to stabilize within a first clock phase (114) of a clock cycle. Thus, the second phase (113) of the clock cycle can be used to determine whether an overflow condition has occurred. For non-time sensitive operations, a precharge device (104) and the discharge device (105) are operably coupled to the dynamic decoding structure (101), while the load (102) is disabled.

Method and apparatus for decoding information within a processing device

A signed arithmetic data processing system (20) detects a multiply (MUL) or a multiply-and-accumulate (MAC) instruction in which a multiplier and a multiplicand each assume their respective maximum negative values. If one or both of the operands is not equal to its maximum negative value, the multiplication proceeds normally, such as in a modified Booth's multiplier/MAC (33). However, if both operands are equal to their respective maximum negative values, the data processing system (20) substitutes a maximum positive constant for the output of the multiplier/MAC (33). This substitution allows the result to be expressed with one fewer bits. The resulting error is very small and becomes insignificant in most digital signal processing algorithms, especially those based on fractional, saturation arithmetic. Alternatively, an extra bit of precision may be achieved for a given hardware size.

Method and apparatus for multiplying two numbers using signed arithmetic

A high-speed barrel shifter (20) includes a shifter array (25) having a matrix of transistors (40) located at intersections of rows and columns of the matrix (40). The rows and columns alternately function as source and destination terminals. A fill portion (48) fills either a predetermined value or a data-dependent value such as a sign bit into vacated bit positions along rows in a bottom left portion (42). Thus the barrel shifter (20) can perform a data-dependent fill instruction within the shifter array (25) and avoids extra clock cycles associated with post-array processing. In one embodiment, an isolation portion (44, 45) separates a top right portion (41) of the matrix (40) from the bottom left portion (42) along a diagonal (43). The isolation portion (44, 45) isolates transistors in the bottom left portion (42), which are associated with rotates and fills, from transistors in the top right portion (41), which are associated with shifts, according to the direction of the shift.

High-speed barrel shifter

A high-speed adder using a varied carry scheme, such as one of the carry-lookahead (CLA) type (30), includes a plurality of adder groups (32-37) each receiving some bits of two input operands. The adder groups are not identical but instead each adder group reduces a delay which is critical to its order. A least significant adder group (32) reduces a delay from operand input to carry output. A most-significant group (37) reduces a delay from carry input to sum output. Intermediate groups (33-36) reduce a delay from carry input to carry output.

High speed adder using a varied carry scheme and related method

A priority encoder (12) has a most significant bit circuitry (18), a first less significant bit circuitry (20) and a second less significant bit circuitry (22). The priority encoder detects a leading one within a plurality of data bits. Each data bit is associated with a different one of a plurality of input signals. The most significant bit circuitry is coupled to a first one of the input signals and generates a first output signal and a parallel blocking signal. Both of the first output signal and the parallel blocking signal are representative in a first logic state of a leading one associated with the first signal. The first less significant bit cell is coupled to a second one of the input signals and to the parallel blocking signal. The first less significant bit cell generates a second output signal and a less significant carry signal. Both the second output signal and the less significant carry signal are representative in a first logic state of a leading one associated with the second input signal. The second less significant bit cell is coupled to a third one of the input signals, to the parallel blocking signal and to the less significant carry signal. The second less significant bit cell generates a third output signal representative in a first logic state of a leading one associated with the third input signal.

Priority encoder and method of operation

An absolute value decoder for decoding an absolute value of an input number in two's complement format. The absolute value decoder receives the input number and inverts each bit. Each bit and each inverted bit are provided to a plurality of columns, and each of the plurality of columns predecodes a unique value of the input number. A precoded signal is precharged during a precharge period and subsequently discharged in response to corresponding bits in the input number not matching the unique number corresponding to the predecoded signal. A grouping portion combines sets of two signals corresponding to a negative number and a positive number of a given absolute value, and provides output signals in response. In another embodiment, columns of transistors provide the predecoded signals for ranges of numbers which can be grouped further so that the absolute value decoder functions as a range detector.

Absolute value decoder

A data processing system has a bus meter, a memory capable of transferring operands requested by the bus master, and a cache for temporarily storing a selected number of the most recently transferred operands. If the memory provides an operand or a portion thereof which is insufficient in size or alignment to fill a complete entry in a line in the cache, the bus master automatically transfers additional operands adjacent in the memory to the requested operand sufficient to fill that entry.

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Austin, TX, United States of America

Donald C Anderson