International Business Machines Corporation

Donald B Mooney

Chi Shih Chang

Majid Ghafghaichi

John Balyoz

Teh-Sen Jen

John A Palmieri

Barry C Fox

Joseph M Mosley

George J Jordy

A circuit and method for generating a read complete signal for a high speed densely packaged monolithic memory is disclosed. The memory is designed to utilize an externally generated address valid signal which indicates that the address to the memory is valid. The receipt of the address valid signal sets a set/reset latch and starts the memory. The addressed memory cells are sensed. When at least one memory cell has data at its output below a threshold, the data are said to be unstable and the set/reset latch is then conditioned to be reset. When the data sensed by all the sensing circuits are stable, a signal is sent to the set/reset latch to cause it to be reset. The resetting of the set/reset latch causes an output thereof to change state. This state change comprises the read complete signal which is used to determine the read cycle time of the memory and may also be used in diagnostic tests of the memory.

Read complete test technique for memory arrays

Master image chip organization technique or method

Disclosed are improved LSI semiconductor design structures termed 'Master Image Chip Organization Techniques'. Utilizing the technique provides increased density and optimized performance of semiconductor devices, circuits, and part number functions. In accordance with the disclosed Master Image Chip Organization Method the semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of LSI part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. In addition, the master image wiring structure provides a means for personalizing power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and performance.

Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices. In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.

LSI Semiconductor device and fabrication thereof

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Poughkeepsie, NY, United States of America

Donald B Mooney