Lockheed Martin Corporation

Unisys Corporation

Sperry Corporation

Sperry Rand Corporation

Donald B Bennett

Steven Allen Murphy

Lee T Thorsrud

Brian Ralph Larson

Leo John Slechta, Jr

Thomas W Petschauer

Thomas Ormond Wolff

Steven Allen Murrphy

John T Rusterholz

James R Hamstra

John W Esch

Larry Don Anderson

Charles J Homan

Lowell E Brown

Robert J Malnati

An expandable network constructed from a plurality of identical network fabric cards which uses a plurality of selected row address bits to route connection paths between adjacent columns of interconnecting switches and a software algorithm for implementing a network of any whole number power of 2 rows or ports by assigning numbers of the network switches and attached nodes are described.

Single-type fabric card networks and method of implementing same

The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, point-to-point, unidirectional links. It is to serve high-performance multiprocessor systems. A number of key elements are defined as part of the protocol for SCI. These include: (a) command.old which is a bit in transmitted packets for detecting stale packets to discard; (b) idle.cc which is an idle bit to be inserted between packets for detecting lost packets which toggles when the idle bit has circulated around the ringlet; and (c) idle.ac which is an idle bit which toggles when all operational nodes have had an opportunity to transmit. In addition, SCI contemplates the implementation of a number of different types of resets, including power reset, upon read or apparent loss of power for more than a second and linc reset for clearing circuits but not changing error count registers in the system. An implementation of SCI for a switching network which does not contain full agent switches (i.e., switches that have queues), as contemplated by SCI is disclosed which extends the utilization of the above-noted key elements. This implementation provides for a substantial reduction in the complexity, size, power and costs of the network. The network may be expandable in that it can service more than the current number of required operational rings which have at least one scrubber node and may have one or more other functional nodes therein, while handling misrouted packets by providing recirculation conductive connections to all input and output ports of the network that are not connected to such operational rings.

Initialization of switching networks for use with a scalable coherent

The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, point-to-point, unidirectional links to high-performance multiprocessor systems. A system is provided for routing packets with a plurality of data bits and target identity code bits through a packet routing switching network. The packets are transmitted from source nodes through the switching network to target nodes that are designated by the target identity code bits. Operational rings are used to link output ports of switches of the output stages to input ports of switches of the input stage wherein each operational ring is identified by ring identity code bits associated with the input stage switches of the operational rings and has at least one node which is capable of performing a function with the data. Recirculation rings are used to link output ports of switches of the output stage to input ports of switches of the input stage. The recirculation rings have no functional nodes in them. Each output port of the output stage switches is coupled to either an operational ring or to a recirculation ring, and the packets are transmitted from source nodes through the operational rings. In the event any of said packets are misrouted, then the packets are transmitted through the recirculation rings or through the operating rings that do not contain the designated target nodes until the packets reach their respective designated target nodes.

Recirculation routes in switching networks used with scalable coherent

The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, unidirectional links to high-performance multiprocessor systems. Key elements of the protocol for SCI include: (a) a 'new/stale' bit which is generated in a data packet for detecting stale packets to discard; (b) an idle.cc which is an idle bit to be inserted between packets for detecting lost packets which toggles when the idle bit has circulated around the ringlet; and (c) a scrubber node in each operational ring of an SCI network which toggles 'new/stale' bits from a 'new' state to a stale state when they are received at the scrubber node. The 'new/stale' bit is also set to a 'new' stale bit when a packet is generated in a source node in a first operational ring for transmission to a target node in a second operational ring. A scrubber node is located as the first node of each operational ring of the network. The new/stale' bit and the idle circulation (idle.cc) is used to keep track of misrouted and lost packets. Each of a plurality of switches of the switching network is assigned to one of a plurality of rows of the switches and to one of a plurality of stages of the switches. Each of the switches has a plurality of input ports and output ports associated therewith. Input ports are coupled to the switches of the input stage, and output ports equal in number to the number of input ports are coupled to the switches of the output stage. The number of switches in a row is equal in number to the number of stages of the switching network. The packets are transmitted from the input ports to the output ports through operational rings that are connected thereto until each of the packets reaches a designated target node.

Detection of lost packets in switching networks used with scalable

The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, point-to-point, unidirectional links to high-performance multiprocessor systems. Key elements of the protocol for SCI are the (a) idle.cc which are idle bits circulation to be inserted between packets transmitted in an SCI network for detecting lost packets which toggles when the idle bit circulation has circulated around the ringlet; and (b) idle.ac, or allocation bit which is a bit in a group of transmitted idle bits which toggles when all operational nodes in an SCI network have had an opportunity to transmit their data packets. All switches accumulate transitions of the allocation bits to a value that is different from the current remembered allocation value on each enabled input port. If the network is out of allocation bit synchronization at a switch when a second transition of allocation bit occurs on an input port of the switch, the transition is ignored. The switch declares agreement when all input ports have made at least one transition even though the current allocation bit values at the input ports are not in agreement. This procedure allows rows that are one idle allocation value behind to advance their value while preventing the other rows from advancing their value, which enables resynchronization of idle allocation values after network idle allocation synchronization has been lost. All non-output stage switches toggle the current value of the allocation bit when all enabled output ports of the switch have transmitted the current allocation bit value and all enabled input ports have transitioned as explained above. This guarantees that the current agreement is broadcast on all output ports before a new value allocation can be accepted.

Allocation of node transmissions in switching networks used with

The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, unidirectional links to high performance microprocessor systems. Key elements of the protocol for SCI include: (a) a 'new/stale' bit which is generated in a data packet for detecting stale packets to discard; (b) a scrubber node in each operational ring of an SCI network which toggles 'new/stale' bits from a 'new' state to a stale state when they are received at the scrubber node. In addition, valid ring identity code bits are used to identify operational rings and target identity code bits are used to identify the intended designated target mode of each packet. Packets are transmitted from input ports to output ports of the switches and through operational rings of the network that are connected until each of the packets reaches a designated target node. Each of the packets includes a 'new/stale' bit which is set to a 'new' state when a packet is generated in a source node in a first operational ring for transmission to a target node in a second operational ring. The target node may be the same as the first node. Scrubber nodes receive the packets and toggles a 'new/stale' bit that is set to a 'new' state to its 'stale' state at the output of the scrubber node. Ring identity code bits at each switch of the input stage are used to identify each of the operational rings. Target identity code bits included in each packet are compared with ring identity code bits that are associated with the input ports of the input stage switches. The 'new/stale' bit of each misrouted packet is reset to a 'new' state which arrives at an input operational stage switch when a comparison of the target identity code bits and the ring identity code bit does not occur, and otherwise the 'new/stale' bit in each packet is left in a stale state if the comparison does occur. The packet is eliminated at the next scrubber node in an operational ring when its 'new/stale' it is in its 'stale' state.

Identification of new and stale packets in switching networks used with

Multiple clocks are interconnected in a network which is fed and controlled by a clock generator. A delay of one or more clock periods less a fixed amount is imposed between any two such clocks excluding the clock generator, to cause the repeated clock so transferred to occur at the appropriate time in the next cycle. Feedback using such delays assures bounded phase differences among these clocks. Thus, skew bounds can be provided for large numbers of clocks, to provide a bounded delay among multiple clocks. There is inserted in each link between a pair of clock nodes a delay line that delays a propogating clock signal by just enough time to cause the repeated clock to occur at the appropriate time in the next cycle, thereby synchronizing the appearance of that clock signal at the various nodes. Self-oscillation of the system, if the clock generator is removed, is avoided by having the delay between any two directly connected nodes be greater than one period of that clock generator.

Apparatus and method for residual error clock skew bound, and clocking

A tightly coupled data processing system having high performance characteristics, including at least one general purpose host processor coupled to host processor ports of a High Performance Storage Unit, and a Scientific Processor directly coupled to scientific processor ports of the High Performance Storage Unit is described. The Scientific Processor is under task assignment control of the host processor and shares the same memory space as the host processor, and thereby provides the tight coupling without need of dedicated memory or caching. Provision is also made for the Scientific Processor to share the virtual address space of the host processor. A tightly coupled system is also disclosed wherein a plurality of general purpose host processors are each coupled to one or more High Performance Storage Units, and a Multiple Unit Adapter is utilized to couple an associated Scientific Processor to all of the High Performance Storage Units. Each Scientific Processor includes a parallel operable scalar processor module and a vector processor module.

Tightly coupled scientific processing system

A Layered Network system may provide varying cost from order NlogN low-cost networds, to completely-routing, fully-Layered networks with cots of order Nlog .sup.3 N. Layered networks are composed of switches and point-to-point connections between them. These networks establish connections from requestors to responders by relaying 'requests' through the switches. Each switch has built-in control logic to route requests and responses. The switch setting is determined using the comparison of the request with the request's current location in the network, and with locally competing requests. To provide distributed routing without a centralized controller, each switch routes the requests using only the information contained in the requests that switch handles. The switch setting is remembered in order to route the responses on the same paths as the associated requests, but in the reverse direction.

Layered network

A bus error detection system is used to detect binary bus error signals. The bus lines include an odd parity line and an even parity line. A clock means provides at least two clock signal phases. An activatable driver drives both of the odd and the even parity lines to the same predefined logic level each time a first clock signal phase occurs. A parity checker coupled to the drive checks during a second clock signal phase the parity of the binary signals which appeared on said bus lines during a preceding first clock signal phase. The driver then drives either the odd or the even parity lines to a predefined logic state according to the parity determined by the parity checker during the second clock signal phase. A verification circuit verifies that only one of the odd and the even parity lines has been driven to a predefined logic state during said second clock phase, and that of both the odd and the even parity lines have been driven during said first clock signal phase to the same predefined logic level.

Bus error detection employing parity verification

A bus arbitration system comprising a plurality of bus lines and a clock which produces first and second phrases in which a drive generates a first logic state during the first phase to precharge the capacitance associated with the bus lines and generates either first or second logic state during the second phase. Also, a bus interface is described in which different types of information are transmitted during different phases.

Versatile interconnection bus

A digital system employing adaptive voting circuitry to improve its fault-tolerance receives an input data bit from each of a number of input data sources. The adaptive voting circuitry has a separate section for each of the input devices which has a weight register that stores an initial weight value which determines the voting strength of the associated input device. The weight values are multiplexed through to a voting circuit which also receives the input data bits. If an input data bit is a logic '1' the weight value of the input data device that supplied this '1' signal is added to the weight values of all other input data devices that supplied '1' data bits. If the data bit from a particular input device is a logic '0', then its weight is added to the weight values for other input data devices which supplied logic '0''. Accumulative voting then takes place via adders in the voting circuit which determines whether the correct output bit should be a logic '1' or a logic '0'. After the correct output bit is obtained, it is compared with the input bits supplied by the different input data devices, and the stoned weight values associated with each of these are decremented if the input device supplied a data bit that did not conform to the correct output bit, or alternately they are incremented if it did.

Digital adaptive voting

A method of and apparatus for encoding computer program instructions and data greatly reduces the total storage requirements. Upon compiling each computer program segment, statistics are generated regarding the frequency of use of each unique program operator and each unique program operand. The operators and operands are encoded using the information theoretic encoding technique. A conversion table is also prepared which enables the object computer to translate the encoded operands and operators during that time when the computer program segment is being executed. Apparatus within the object computer decodes the encoded operands and operators using the conversion tables enabling execution of the computer program segment.

Reflexive utilization of descriptors to reconstitute computer

Bidirectional communication upon a high performance synchronous (25 MHz line transfer rate) parallel digital communication bus interconnecting large numbers (up to 256 along 1 meter of bus) of very large scale integrated (VLSI) cirucit devices is supported by VLSI wired-Or driver/receiver (D/R) circuit elements synergistically operative under a two-time-phase bus electrical protocol for bus drive. During a first phase of approximately 10 nanoseconds all interfacing driver circuits additively drive, or pull-up, connected bus lines to a +3 v.d.c. logical High condition. During a second phase of approximately 20 nanoseconds during each 40 nanosecond cycle time D/R circuits present high impedance to charged bus lines for maintenance of such logical High and transmission of a logical '0', or else one or more D/R circuits drain line charge toward 0 v.d.c. for transmission for a logical '1'. Two point driver to receiver, wired-OR, broadcast, and/or eavesdrop communication are supported for bus lines.

VLSI Wired-OR driver/receiver circuit

A virtual address translator comprises a content addressed memory and a word addressed memory. A task name and subsegment number from a virtual address supplied by a processor are employed as a key word to search a content addressed memory and read out a subsegment descriptor if the key word is matched. The subsegment descriptor includes an absolute base address which is added to a deflection field to obtain an absolute memory address. The memory address is applied to a memory to permit transfer of a word between the processor and the memory. The processor may present any one of several task names depending upon whether the memory reference is made for an instruction or data for the processor, or for an instruction or data for an I/O connected to the processor. Bounds, residency and access privileges are checked using the subsegment descriptor. If a search of the content addressed memory reveals that the desired subsegment descriptor is not in the word addressed memory, the translator obtains the descriptor from memory and then generates the desired absolute memory address. The translator is provided with circuits generating values which indicate the efficiency of its operation. Controls are provided for selecting any one of several widths for the subsegment and deflection fields of virtual addresses received from the processor.

Growing community of inventors

Burnsville, MN, United States of America

Donald B Bennett