Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Donald A Williamson

Debendra Das Sharma

John F Shelton

John Alan Wickeraad

Ashish Gupta

Edward M Jacobs

John R Obermeyer

A method and apparatus using a clock generator with sequential logic to align the phase of a first clock generated on a receiving integrated circuit (IC) chip to a second clock received by the receiving IC chip. One embodiment of the invention involves a method for aligning the phase of a first clock relative to the phase of a second clock, wherein the first clock is provided by a clock generator in a data processing system. The method includes sampling the second clock with a sampling clock, detecting an edge on the second clock, and stretching the first clock to align the phase of the first clock relative to the phase of the second clock. A second embodiment of the invention involves a data processing system including a transmitting chip, a receiving chip, and a clock generator for aligning the phase of a first clock relative to the phase of a second clock, wherein the second clock is received by the receiving chip. The clock generator includes a sampling circuit to sample the second clock with a sampling clock, a circuit to detect an edge on the second clock, and a sequential logic circuit to stretch the first clock to align the phase of the first clock relative to the phase of the second clock and control the clock generator.

Apparatus and method to align clocks for repeatable system testing

An apparatus and method for an improved asynchronous communication channel between a transmitter and a receiver having separate clocks. The invention provides a simple implementation that solves both the overflow and the underflow problem using the same mechanism, and reduces complexity by elimination of the control split between the two clock domains. A first embodiment of the invention is a method for preventing packet underflow and packet overflow for packets sent across an asynchronous link between a transmitter and a receiver, including a buffer that can store a number of packets greater than an ideal number of packets. The method includes sending a predetermined number of drop-me warning packets and sending one or more drop-me packets from the transmitter to the receiver, receiving the predetermined number of drop-me warning packets and the one or more drop-me packets in the buffer, compensating for packet overflow when the number of packets is greater than the ideal number of packets in the buffer by skipping at least one drop-me packet, and compensating for packet underflow in the buffer when the number of packets is less than the ideal number of packets by stalling access to the buffer for one or more clock cycles. A second embodiment of the invention is an asynchronous link for packets sent between a transmitter having a first clock and a receiver having a second clock, including a buffer to receive the first clock from the transmitter and receive from the transmitter a number of packets equal to or different to a predetermined ideal number of packets, a write pointer, and a read pointer, and a read pointer control circuit to change the read pointer, wherein the buffer can receive drop-me packets, and the read pointer can skip a drop-me packet in the buffer.

Method and apparatus for preventing underflow and overflow across an asynchronous channel

A function for verifying an asynchronous boundary behavior of a digital system. The asynchronous boundary is formed at a coupling between a first series of registers clocked by a write clock (the write domain), and a second series of registers clocked by a read clock (the read domain). A delay register and multiplexer are inserted after a predetermined register within the digital system, where the predetermined register and delay register are clocked by the same clock. The output of the predetermined register is coupled to both the first input of multiplexer and a first input of the delay register. The delay register is coupled to the second input of the multiplexer. A selector is coupled to the multiplexer for selecting which of the two multiplexer inputs to pass to subsequent registers in the digital system. By inserting the delay register/multiplexer at or after the asynchronous boundary, any signal level uncertainty present between the read domain and the write domain is captured and propagated through the digital system.

Verification of asynchronous boundary behavior

A scan testable circuit in a computer system is controlled by using a single scan clock and a fixed delay circuit to realize the required scan clocks and a required scan mode enable signal. The multiple signals are generated from a subset of signals supplied to the scan control signal generation circuit. System data and scan data are routed through a multiplexer to test or initialize lines and circuitry. A scan control signal generation circuit according to the invention has the advantage of eliminating as excess a scan mode enable signal originating elsewhere in the computer system, thereby eliminating unneeded signal traces while minimizing the number of pins required for this function. In a first embodiment, a scan mode enable signal is generated from one of two scan clocks. In a second embodiment, both scan clocks and the scan mode enable signal are generated from a single source clock.

Apparatus for generation of scan control signals for initialization and

A scheme for improving the decoding time of macroinstruction opcodes in a programmed computer is provided. By having a direct Instruction Jump Table responding to macroinstructions and a pipelined Address Jump Table responding to the same macroinstructions simultaneously, larger sequences of microinstructions are decoded in a minimum number of microcycles, thus resulting in a faster operating programmed computer.

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Cupertino, CA, United States of America

Donald A Williamson