Freescale Semiconductor,inc.

Digital Equipment Corporation

Compaq Information Technologies Group, L.p.

Donald A Priore

Edward J McLellan

David J Husak

James Arthur Farrell

Dilip K Bhavsar

Mark A Sankey

Andrew T Brown

Andrew D Funk

Paul Schmitt

Thomas B Brightman

John F Brown

Tina P Zou

An integrated circuit () for use in processing streams of data generally and streams of packets in particular. The integrated circuit () includes a number of packet processors (), a table look up engine (), a queue management engine () and a buffer management engine (). The packet processors () include a receive processor (), a transmit processor () and a risc core processor (), all of which are programmable. The receive processor () and the core processor () cooperate to receive and route packets being received and the core processor () and the transmit processor () cooperate to transmit packets. Routing is done by using information from the table look up engine () to determine a queue () in the queue management engine () which is to receive a descriptor () describing the received packet's payload.

High speed and high throughput digital communications processor with efficient cooperation between programmable processing components

Digital communications processor

A self-repair method for a random access memory (RAM) array comprises writing a value to the memory array, reading a value from the memory array and comparing the read and write values to identify faulty memory cells in the memory array. An address of a newly-discovered faulty memory cell is compared to at least one address of at least one previously-discovered faulty memory cell. The address of the newly discovered faulty memory cell is stored if a column or row address of the newly-discovered faulty cell does not match any column or row address, respectively, of a previously-discovered faulty memory cell. Flags are set to indicate that a spare row or a spare column must replace the row or column, respectively, identified by the address of the previously-discovered faulty memory cell, if the row or column address of the newly-discovered memory cell matches the respective row or column address of the previously-discovered faulty memory cell. Spare rows and columns that have been indicated by the flags as requiring replacement are allocated to replace faulty rows and columns respectively. The remaining spare rows and columns whose row and column addresses respectively have been stored are then allocated. Furthermore, the RAM is flagged as unrepairable if an insufficient number of spare rows or spare cells remain to replace all of the rows or columns containing faulty cells.

Embedded RAM with self-test and self-repair with spare rows and columns

A technique for encoding failing bit addresses in a memory array with redundant portions such as column slices. The address or other identification of a column slice or other portion of a memory array is identified to test logic using a wired-OR bus configuration. The technique assigns a code consisting of predetermined number of asserted bits to each portion of the memory. If a failure condition is detected, the code associated with that portion is asserted onto the bus. Because the code for each memory portion always has a given number of asserted bits, a multi-bit failure situation can be distinguished from a single bit failure situation by counting the number of bits asserted.

Encoding of failing bit addresses to facilitate multi-bit failure detect

Growing community of inventors

Maynard, MA, United States of America

Donald A Priore