Corsair Memory, Inc.

Cypress Semiconductor Corporation

Cosair Memory, Inc.

Multichip Technology

Donald A Lieberman

Daniel R Solvin

John J Nemec

Martin Emil Mueller

John Beekley

Michael Gerard O'Connor

Monitoring parameters of memory modules is described. According to certain embodiments, one or more parameters on respective memory modules are monitored. Corresponding parameter information is transmitted away from the respective memory module to a device that is external to the respective memory modules.

Monitoring memory module parameters in high performance computers

Monitoring parameters of memory modules is described. According to certain embodiments, one or more parameters on respective memory modules are monitored. Corresponding parameter information is transmitted from the respective memory module to a device that is external to the respective memory modules.

An ATX compatible power supply unit having at least one DC power outlet and at least one DC power cable, the DC power outlet configured to support nominal contact resistances of less than 2.5 milliohms per contact or the DC power cable configured to support series resistances of less than 4 milliohms per linear foot of individual conductor is disclosed.

DC interconnect scheme for PSU

Power supplied to a memory module is provided. A first voltage is supplied to a first power distribution pathway, the first voltage being from a voltage supplied to a printed circuit board on which the memory module resides. A second voltage is generated, the second voltage being generated by a voltage regulator. The second voltage is supplied to a second power distribution pathway.

Boosting memory module performance

An ATX compatible power supply unit having a main printed circuit board and at least one connector printed circuit board that includes at least one outlet connector for use with a DC modular cable, the at least one connector printed circuit board is connected to the main printed circuit board with connectors other than bare or insulated wires to allow high currents to be transferred between the at least one connector printed circuit board and the main printed circuit board at low voltage drops is disclosed.

PCB interconnect scheme for PSU

A memory system includes a main memory and a memory controller, the main memory including at least one block which has a plurality of banks. The memory controller includes a plurality of data channels each of which can access at least one bank in the main memory. Each data channel comprises a write first-in-first-out (FIFO) buffer for efficiently supporting cache purge operations and normal write operations, and a reflective write FIFO buffer for efficiently supporting coherent read with simultaneous cache copyback operations. The memory controller selects the proper FIFO or FIFOs depending on the type of data transaction, and selects the proper channel or channels depending on the system bus size, the data transaction size, and the status of cache FIFO(s). The memory system can efficiently support data transactions having different data lengths or sizes from a byte to a long burst. The memory system can support different bus and processor systems and different data transactions in a highly efficient manner.

Memory system and method for selecting a different number of data

A memory system includes a memory and a controller coupled to the memory and a system bus. The controller is configured to receive a bus clock and control signals over the system bus and to provide memory control signals with a predetermined timing resolution to the memory. The controller includes a bus clock frequency multiplication circuit for generating an internal clock signal which is used to generate the memory control signals, and a programmable timing register for storing timing intervals of the memory control signals. The bus frequency multiplication circuit generates the internal clock signal by multiplying the frequency of the bus clock by a bus frequency multiplication factor which is selectively chosen to set the predetermined timing resolution for the memory control signals to a nearly constant value independent of the frequency of the bus clock. The bus frequency multiplication circuit may comprise a phase locked loop.

Dynamically configurable memory system having a programmable controller

A memory system includes a main memory and a memory controller. The main memory includes at least one block which has a plurality of banks. The memory controller includes a plurality of data channels each of which can access at least one bank in the main memory. Each data channel comprises a write first-in-first-out (FIFO) buffer for efficiently supporting cache purge operations and normal write operations, and a reflective write FIFO buffer for efficiently supporting coherent read with simultaneous cache copyback operations. The memory controller selects the proper FIFO or FIFOs depending on the type of data transaction, and selects the proper channel or channels depending on the system bus size, the data transaction size, and the status of the FIFO(s). The memory system can efficiently support data transactions having different data lengths or sizes from a byte to a long burst, and the timing resolution of the memory is enhanced regardless of the bus clock frequency. During burst transactions, the channels can run in an alternating fashion. During reads, the data is error-checked before being output to the system bus. The memory system can support different bus and processor systems and different data transactions in a highly efficient manner.

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San Jose, CA, United States of America

Donald A Lieberman