Cypress Semiconductor Corporation

Donald A Krall

S Babar Raza

Roger J Bettman

Anita X Meng

Hagop A Nazarian

Donald Y Yu

Christopher S Norris

Khaldoon S Abugharbieh

The present invention provides an integrated parallel and serial programming interface that can be selected between either a parallel programming mode or a serial programming mode. The present invention provides a control logic circuit for selecting between the parallel and serial modes. The present invention also includes a parallel and serial detection circuit. The control logic sends a signal to an interface circuit that selects between a serial programming mode and a parallel programming mode based on the outputs of the parallel and serial detection circuits.

Design architecture for a parallel and serial programming interface

The present invention provides a clocking circuit allowing individual macrocells in a particular macrocell block of a CPLD to use different polarities of the same clock. The input clock pin can now drive all the macrocells directly, which can eliminate additional buffering states and improve the clock to out timing, Tco, by (for example) 300 ps. The clocks are presented directly to the clock selection multiplexers for each macrocell. Additional functioning may be realized by implementing additional configuration bits inside the clocking architecture.

Clock distribution architecture and method for high speed CPLDs

The present invention provides a circuit for supplying a verifying reference and measurement voltage for use in verifying the programming of a programmable cell. The present invention provides the verifying reference and measurement voltage through internal circuitry on the cell and eliminate any requirement for an externally provided reference voltage. The verifying voltage is provided by modifying the programming voltage. The programming voltage is stepped down or stepped up through the use of internal circuitry to provide the reference and measurement voltage.

High voltage reference and measurement circuit for verifying a

A high-speed programmable macrocell includes structure sufficient to implement a combined in the combinatorial storage signal path when the macrocell is operated in the combinatorial, and storage modes of operation. The macrocell includes, a master circuit (including a polarity multiplexer), and a slave circuit (including a transmission gate). The polarity multiplexer is responsive to input data for generating an output signal corresponding to one of a true and complemented state of the input data, according to a polarity configuration bit. The master circuit stores the multiplexer output in response to a low-to-high transition of a clock signal when operating in the storage mode. The master circuit, when in the combinatorial mode, will always pass the multiplexer output therethrough. The transmission gate is coupled to the master circuit and, in the storage mode, will block the output of the master circuit from passage therethrough when the clock is low, but will pass such output therethrough when the clock is high. The transmission gate will always pass the master circuit output when operating in the combinatorial mode. The slave circuit generates output data having true and complemented states in both the storage and combinatorial modes. When in the combinatorial mode, the slave circuit, which, in addition to the transmission gate includes an inverter and a tristate buffer connected in a feedback arrangement, stores and outputs data when the clock is low, based on the data provided to it when the clock is high.

Growing community of inventors

Cupertino, CA, United States of America

Donald A Krall