Hrl Laboratories, LLC

The Boeing Company

Donald A Hitko

Zhiwei A Xu

James Chingwei Li

Michael W Yung

Peter Petre

Yen-Cheng Kuan

Cynthia D Baringer

Susan L Morton

Carson R White

Pamela R Patterson

Yakov Royter

Hasan Sharifi

Jose Cruz-Albrecht

Joseph S Colburn

Albert E Cosand

Alan E Reamon

Chan-Tang Tsen

Daniel Yap

Oleg M Efimov

Joseph F Jensen

Mary Y Chen

David S Matthews

Randall White

Jason W May

Ining Ku

A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.

Multiplexing sample-and-hold circuit

A transistor having an emitter, a base, and a collector, the transistor includes a substrate, a collector contact, a metallic sub-collector coupled to the collector contact, and the metallic sub-collector electrically and thermally coupled to the collector, and an adhesive layer between the substrate and the metallic sub-collector, the adhesive layer bonded to the substrate and in direct contact with the substrate and bonded to the metallic sub-collector and in direct contact with the metallic sub-collector, wherein the adhesive layer comprises an electrically conductive material.

Metallic sub-collector for HBT and BJT transistors

A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals. The proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies. The DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal-to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions.

Interleaved sigma delta modulator based SDR transmitter

An asynchronous pulse domain to synchronous digital domain converter for converting pulse domain signals in an input asynchronous pulse domain data stream to synchronous digital domain signals in a data output stream. The converter comprises a plurality of counters arranged in a ring configuration with only one counter in the ring being responsive at any given time to positive and negative going pulses in the input asynchronous pulse domain data stream, each counter, when so responsive, counting a number of time units between either (i) a positive going pulse and an immediately following negative going pulse or (ii) a negative going pulse and an immediately following positive going pulse, the counts of the counters when so responsive being synchronously converted to synchronous digital domain signals in the data output stream. The disclosed asynchronous pulse domain to synchronous digital domain converter can be used with spike domain signals if desired.

Asynchronous pulse domain to synchronous digital domain converter

A delta sigma modulator which has improved the dynamic range. The &#x394;&#x3a3; modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the &#x394;&#x3a3; modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop.

Interleaved &#x394;-&#x3a3; modulator

An agile transceiver including a receiver channel that includes an input, a coarse tracking filter coupled to the input, the coarse tracking filter having a set of at least two bandpass filters for filtering signals from the input into at least two coarse pass bands, a mixer coupled to an output of the coarse tracking filter, a selected local oscillator coupled to the mixer for mixing with the output of the coarse tracking filter and shifting a desired coarse pass band to near a base band, a fine tracking filter for filtering the shifted and desired coarse pass band to a fine pass band, and a band pass &#x3a3;&#x394; demodulator for converting signals in the fine pass band from analog into digital. The agile transceiver may include a corresponding transmitter channel.

Agile radio architecture

A heterojunction bipolar transistor having an emitter, a base, and a collector, the heterojunction bipolar transistor including a metallic sub-collector electrically and thermally coupled to the collector wherein the metallic sub-collector comprises a metallic thin film, and a collector contact electrically connected to the metallic sub-collector.

Method for forming metallic sub-collector for HBT and BJT transistors

A pulse domain 1 to 2N demultiplexer has a (i) pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of the counters being responsive to leading edges of the pulses in the incoming pulse train and the other one of the counters being responsive to trailing edges of the pulses in the incoming pulse train and (ii) a control logic responsive to the states through which the pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of the pulse domain 1 to 2N demultiplexer.

Dual edge pulse de-multiplexer with equalized path delay

An automatic tuning circuit for matching an antenna to a radio receiver. The automatic tuning circuit includes a tunable non-Foster circuit for coupling the receiver and the antenna; and sensing and feedback circuits for sensing the combined capacitance of the tunable non-Foster circuit and the antenna and for tuning the tunable non-Foster circuit to automatically minimize the combined capacitance of the tunable non-Foster circuit and the antenna.

Wide bandwidth automatic tuning circuit

Disclosed herein is an apparatus for radio frequency digital-to-analog conversion of in-phase and quadrature bit streams. The apparatus may include a plurality of in-phase multiplying cells that receive an in-phase local oscillator signal and a plurality of in-phase bits, a plurality of quadrature multiplying cells that receive a quadrature local oscillator signal and a plurality of quadrature bits, a first output line connected to a first set of the plurality of in-phase multiplying cells and a first set of the plurality of quadrature multiplying cells, and a second output line connected to a second set of the plurality of in-phase multiplying cells and a second set of the plurality of quadrature multiplying cells. Each multiplying cell produces an output signal based on a received input bit. The output signals from each multiplying cell combine in phase on the connected output line.

In-phase and quadrature radio frequency digital-to-analog converter

Optical angle of arrival sensors and methods for determining an angle of arrival of incident light are provided, wherein one sensor includes a focusing lens and an array of lateral-effect position sensing detector (LEPSD) elements. The focusing lens is configured to focus light on the array, wherein each of the LEPSD elements includes an absorber region that absorbs light of a first wavelength range that is focused on the LEPSD elements. Each of the LEPSD elements further includes at least one lateral current conducting layer that has a relatively low sheet resistance.

Optical angle of arrival sensors and methods for determining an angle of arrival of incident light

A method of and circuit for improving stabilization of a non-Foster circuit. The method comprises steps of and the circuit includes means for measuring a noise hump power at an antenna port or an output port of the non-Foster circuit, comparing the measured noise hump power with a desired level of noise power that corresponds to a desired operating state of the non-Foster circuit, and tuning the non-Foster circuit to generate the desired level of noise power to achieve the desired operating state of the non-Foster circuit.

Non-foster circuit stabilization method

A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as 'non-Foster circuits.' The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).

Growing community of inventors

Grover Beach, CA, United States of America

Donald A Hitko