Analog Devices,inc.

Other

Donal P Geraghty

Albert C O'Grady

Dennis A Dempsey

Patrick C Kirby

Colin Gerard Lyden

Eoin Edward English

Mark Murphy

John M Wynne

Tudor M Vinereanu

Denis Martin O'Connor

Colm F Slattery

Alan Gillespie

Michael G Curtin

James F Caffrey

Sean Smith

Patrick F M Poucher

Christopher A Kenny

A device and method are provided to drive piezoelectric elements in haptic applications. In one embodiment, a pattern generator provides user programmable PWM waveforms to a driver. The load of the driver is an inductor in series with the piezoelectric element. The filtration of the inductor in series with the capacitance of the piezoelectric element suppresses the high-frequency components of the PWM pulse train, and recovers a value commensurate with the duty cycle of the PWM pulse train. The resulting waveform across the piezoelectric element is converted to physical motion, thereby creating a haptic effect on a user interface. Advantageously, there is reduced power loss, reduced switching induced noise, and a more haptic rich environment.

Reactive networks to reduce acoustic noise and ensure maximum efficiencies in driving piezoelectric elements in haptic applications

A single chip integrated circuit measuring circuit () for determining a characteristic of the impedance of an external complex impedance circuit () for facilitating characterization of the impedance of the complex impedance circuit () comprises a signal generating circuit () for generating a variable frequency stimulus signal for applying to the complex impedance circuit (). A first receiving circuit () receives a response signal from the complex impedance circuit () in response to the stimulus signal and conditions the response signal. A first analog-to-digital converter () converts the conditioned response signal to a first digital output signal, which is read from the first analog-to-digital converter () through a first digital output port (). The response signal from the complex impedance circuit () is a current signal, and a current to voltage converter circuit () converts the response signal to a voltage signal. A first RMS to DC level converting circuit () converts the AC voltage of the response signal to a DC voltage level, and a fourth multiplexer () selectively applies the voltage response signal or the DC voltage level signal to the first analog-to-digital converter (), depending on whether it is desired that the first digital output signal should be indicative of the phase shift or amplitude change in the response signal relative to the stimulus signal. A second receiving circuit () receives the stimulus signal, and similarly converts the stimulus signal to a second digital output signal for facilitating comparison of the response signal with the stimulus signal.

Measuring circuit and a method for determining a characteristic of the impedance of a complex impedance element for facilitating characterization of the impedance thereof

A multi-channel integrated circuit comprises a plurality of channels (CHto CH). A DAC () is provided in each channel (CHto CH) for converting digital data inputted to the circuit () through an I/O port (). Digital data to be converted by the DACs () is selectively applied to input registers () of each channel (CHto CH) on a digital data bus () under the control of an interface and control logic circuit (). The digital words written to the input registers () are in turn written to DAC registers () through corresponding digital switches () for conversion by the DACs (). A clear code register () stores a clear code for writing to the DAC registers () in response to a clear signal applied to a clear terminal () of the circuit () so that analogue outputs appearing on output terminals () of the channels (CHto CH) are of a predetermined value, typically, zero volts, when the circuit () is set in a clear condition. The clear code is written to the clear code register () through the I/O port () and the interface and control logic circuit ().

Integrated circuit comprising a DAC with provision for setting the DAC to a clear condition, and a method for setting a DAC to a clear condition

A multi-channel circuit () comprising a plurality of on-chip channels (CHto CH), each of which comprises a DAC () for converting digital data into analogue output signals independently of each other under the control of an interface and control logic circuit (). The analogue output signals from the DACs () are outputted on output terminals () of the respective channels (CHto CH). The digital input data and control and address signals for controlling the conversion of the digital data in the DACs () are inputted to the interface and control logic circuit () through an I/O port (). DAC registers () are provided in the respective channels (CHto CH) for storing the digital words to be converted in the corresponding DACs (). Analogue input terminals () are provided for receiving analogue input signals (), for example, analogue signals from external systems which may be controlled by the output signals from the DACs (). A multiplexer () is operable under the control of the interface and control logic circuit () for selectively and sequentially applying the analogue output signals from the DACs () and the analogue input signals from the analogue input terminals () to a monitoring output terminal () for facilitating independent monitoring of the analogue output signals from the DACs (), and the analogue inputs on the analogue input terminals ().

Multi-channel integrated circuit comprising a plurality of DACs, and a method for monitoring the output of the DACs

A signal generator () for generating a square waveform analog voltage output signal comprises an on-chip DAC () which outputs the analog voltage signal on an output terminal (). On-chip first and second programmable registers () store first and second digital words which correspond to the maximum and minimum voltage values of the analog output signal. An on-chip switch circuit () selectively and alternately switches the first and second registers () to an on-chip DAC register () from which the respective first and second digital words are loaded into the DAC () in response to a load DAC signal generated by a control circuit (). The load DAC signal is generated in response to an externally generated LDAC signal in the form of a clock signal which is applied to an LDAC terminal (). A flip-flop () in response to the load DAC signal outputs a control signal on a control line () for alternately switching the first and second registers () to the DAC register (). The frequency of the analog output signal is determined by the frequency of the LDAC signal, and is half the frequency of the LDAC signal.

Signal generation using DAC having selectively switched registers storing output values

A multi-channel DAC having a digital input port ( ) for receiving digital input codes and a plurality of analogue output terminals (OUT to OUTN) on channels (CH to CHN) on which corresponding analogue signals are outputted, comprises a primary DAC ( ) which receives the digital input codes from the input port ( ). Analogue signals from the primary DAC ( ) are selectively and sequentially sampled onto infinite sample and hold circuits (SH to SHN) of the channel (CH to CHN) through primary switches PS to PSN) under the control of a primary control circuit ( ). Each infinite sample and hold circuit (SH to SHN) comprises a secondary DAC ( ) which outputs an analogue signal which closely approximates to the sampled analogue signal from the primary DAC ( ) and which is held on the corresponding output terminal (OUT to OUTN). Secondary digital codes may be selectively applied to the secondary DACs of the respective infinite sample and hold circuits SH to SHN for incrementing or decrementing the analogue signal held on the corresponding output (OUT to OUTN).

Digital to analog converting circuit

An infinite sample-and-hold circuit which employs a DAC and an ADC coupled with a mode control circuit. In acquisition mode, the mode control circuit connects the analog input signal to the ADC. The ADC drives the DAC and when the DAC output equals the analog input, the mode control circuit disconnects the analog input and the DAC drives the output in hold mode. The mode control circuit preferably includes a comparator/buffer circuit including switching circuitry. The ADC is preferably of the successive approximation type. The comparator/buffer is used in two modes: (1) open loop, as a comparator, and (2) closed loop, as a buffer. During acquisition, the comparator mode is used, while in hold mode the buffer mode is used. The utilization of the same amplifier to provide both functions allows cancellation of offset errors otherwise introduced by the comparator and buffer, at least to a first order.

Infinite sample-and-hold circuit

An integrated-circuit (IC) chip formed with a D-to-A converter (DAC) and an amplifier to receive the DAC output and to produce a corresponding signal for an output terminal. The chip includes control circuitry to prevent harmful instability in the signal at the output terminal during times that one or more power supply voltages are changing. The control circuitry includes a voltage-monitoring device which produces a RESET signal when a monitored supply voltage is beyond its nominal operating range. The RESET signal de-activates the amplifier input and output circuits, and following a short time delay after the start of RESET, disables the amplifier by killing the amplifier bias currents. The chip is arranged to receive a RESET signal from external devices, and to produce a RESET signal for any other devices in the system.

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Monaleen, Ireland

Donal P Geraghty