Motorola Corporation

Don W Zobel

Dennis L Welty

W Eric Main

W David Pace

Robert Bruce Davies

Robert B Jarrett

Geoffrey W Perkins

David L Cave

Tony Takeshian

Steven L Harris

A charge pump circuit (10) has been provided for maintaining the currents sunk by each of the bottom current sources (12, 14) substantially equal to the current sourced from a first upper current source (16). The present invention maintains the voltage across a second upper current source (64) that determines the current for the lower current sources to be modified with respect to corresponding changes in the first upper current source wherein these changes in the first upper current source are due to a varying voltage occurring at the output (18) of the charge pump circuit.

Current compensating charge pump circuit

A negative feedback loop, including a two collector I.sup.2 L gate having one collector returned to the input of the gate and forcing a reference current into the other of the two collectors of the gate, is used to match the current at the collector of the injector of the gate to the reference current. The feedback loop further includes a current source for sourcing the reference current and a pair of cascoded emitter follower transistors coupled between the current source and the injector input of the gate such that the feedback loop will regulate the current through the injector to be equal to the reference current. The injector input of the gate of the feedback loop can be coupled to the injector inputs of similar I.sup.2 L gates to be biased therefrom such that the injector currents are well controlled.

Current biasing for I.sup.2 L circuits

An integrated circuit sensor circuit (10) is disclosed which is operable in differential or single-ended modes at DC input potentials which can be below the integrated circuit substrate bias potential (ground). Substrate injection is prevented and the circuit is operable for input signals which can vary relatively widely with respect to the substrate bias potential. This is accomplished even though only a single polarity power supply (+5 volts) with respect to substrate bias potential is used for the integrated circuit. An input stage of an integrated circuit (16) comprises a pair of identical polarity transistors (23, 24) operated in a differential common base mode with an opposite polarity transistor (25) used to supply appropriate bias potential to the common base connection. This prevents substrate injection while maintaining a wide operative range for the sensor circuit. Additional substrate injection preventing circuitry (31) is provided to maintain the collectors of the differential input transistors above the integrated circuit substrate base potential, and input protection circuitry (32-35) is used to limit the magnitude of applied input signals.

Integrated circuit sensor circuit

A Class AB amplifier circuit includes bias circuitry for biasing the output transistor into partial conduction independent of the base-to-emitter voltage of the transistor. The bias circuitry is a simple circuit loop including the output transistor and forms the remainder of the amplifier circuit which can be fabricated in monolithic integrated circuit form. The loop comprises a differential amplifier for providing a substantially constant offset voltage across a pair of terminals between which is connected a current biasing component. The current biasing component is connected in series with the output transistor to produce a small quiescent current to flow therethrough, the value of which is independent of the transistor's characteristics.

Bias circuit which is independent of output device voltage

A circuit for limiting the magnitude of current sourced from a first load circuit to a second load circuit to a predetermined value. The circuit includes a current sourcing circuit for sourcing current from the first load circuit to the second and a feedback circuit which is responsive to the magnitude of the current sourced to the second load circuit reaching the predetermined value for supplying any additional current that the second load circuit may require while inhibiting additional current from being sourced from the first load circuit.

Current limiter circuit

A balanced multiplier circuit for a subscriber loop interface circuit (SLIC) which provides both loop current to a two-wire bidirectional subscriber loop and suppression of longitudinal signals generated at the two-wire loop input to the SLIC while maintaining the midpoint load voltage at half the available power supply voltage applied to the SLIC.

Balanced current multiplier circuit for a subscriber loop interface

A relaxation oscillator which is suited for fabrication as a monolithic circuit and which uses a parallel resistive capacitive frequency determining network wherein a capacitor is charged and discharged between an upper and lower voltage level. As the capacitor is charged to a potential exceeding a first threshold voltage level supplied to a comparator switch, the operating state of the comparator is caused to switch. A current detecting circuit is included which detects a current that is proportional to the charging current supplied to the capacitor from a charge circuit. As the proportional current decreases in value below a predetermined level due to the capacitor being charged to the upper voltage level the current detecting circuit is disabled which actuates a control circuit for switching the threshold voltage applied to the comparator to a lower level. The actuated control circuit also disables the charge circuit such that the capacitor discharges to the lower voltage level at which time the comparator switches states to disable the control circuit whereby the threshold voltage level is switched to the first level. Thereafter, the charge circuit is enabled to enable the current detecting circuit and to charge the capacitor to the upper voltage level.

Precision differential relaxation oscillator circuit

A two transistor voltage reference circuit controls the ratio of the current densities of two transistors by a negative feedback loop. A voltage corresponding to the difference in the base-to-emitter voltages of the two transistors is developed which has a positive temperature coefficient (TC) and which is connected in series with the base-to-emitter voltage of one of the two transistors having a negative TC. The circuit parameters are selected so that the resultant combined voltage has a predetermined, composite TC. A zener diode is included in the negative feedback loop and arranged to have a TC which cancels the predetermined composite TC to develop a reference voltage having a high magnitude that has minimal variation with temperature change.

Solid-state voltage reference providing a regulated voltage having a

The disclosed amplifier includes first and second gain stages and first and second frequency compensating capacitors. The second gain stage has a first high impedance node coupled to the first gain stage, a second high impedance node, a first circuit coupled between the first and second high impedance nodes, a third high impedance node, and a second circuit coupled between the second and third high impedance nodes. The impedances at the first, second and third high impedance nodes are a function of frequency and the impedance at the second high impedance node is lower at any given frequency than the impedances at the first and third high impedance nodes. The first frequency compensating capacitor is coupled between the first and third nodes and the second frequency compensating capacitor is coupled between the third and second nodes.

Frequency compensated high frequency amplifiers

A variable dwell ignition system comprising a circuit responsive to changes in engine RPM for causing the dwell time of the ignition system to be varied accordingly. The circuit is adapted to be connected to a sensor coil to receive ignition timing signals developed thereacross which are generated in timed relationship to the engine operation. The circuit provides for changing the direct current (DC) level about which the ignition signals are generated such that a threshold level is varied. As the threshold level is varied the dwell time of the system is varied respectively.

Threshold circuit suitable for use in electronic ignition systems

Fail safe circuitry of an anti-skid control apparatus for a brake system of a motor vehicle. The fail safe circuitry is rendered in a monolithic integrated circuit chip and includes apparatus for sensing the power consumed by said chip and apparatus for decoupling said chip from the power source for preventing its thermal destruction when the power consumed reaches a predetermined level. The chip also includes apparatus for precisely timing the time duration of a brake release provided by the anti-skid control apparatus and generating a latch signal to disable said anti-skid control apparatus to limit the brake release duration within a predetermined time duration.

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Tempe, AZ, United States of America

Don W Zobel