Zilog, Inc.

Don Smith

Monte J Dalrymple

Lois F Brubaker

Phillip D Verinsky

A number of stand-alone devices are connected in a sequence in a predetermined order for reading information from a bus. The devices read information from the bus one at a time and in the predetermined order in response to a signal.

System with devices connected in sequence to receive information in a

A control register residing in a circuit chip stores a set of hardware parameters which exercise programmable control over circuits in the chip to allow for various critical hardware options. A plurality of chips and their control registers may be addressed and written individually by a processor through normal bus access. Each control register is permitted to be written only once, shortly after reset. A circuit, in response to a reset signal and a chip select signal, enables the individual control register for writing, and further, in response to a write strobe, latches data from the data bus into the register and soon afterwards ceases enabling the register for further writes. The various hardware options responsive to the hardware parameters include allowing for various bus interfaces, trimming the time constant of an analog RC circuit which provides internal bus timing strobes, switching internal timing strobes to external pads for output, switching external timing strobes from external pads to replace the internal strobes, and floating the outputs of all output pad drivers for junction leakage tests.

Device and method for programming critical hardware parameters

A bus-oriented integrated circuit chip containing devices such as Receive and Transmit FIFO's further includes a testing circuit for testing normally inaccessible internal nodes in a FIFO device. The testing circuit includes test mode control register for storing the externally supplied test addresses of selected internal nodes of a FIFO device. A decoder, responding to a test command from a host microprocessor, selects the test addresses from the test mode control register and supplies them instead of other addresses to an internal address bus. A test decoder responds only to the test addresses on the internal address bus for enabling the transfer of data between the selected internal nodes and a data bus, thereby enabling bus access of the normally inaccessible internal nodes of a FIFO device.

System for testing internal nodes in receive and transmit FIFO's

A peripheral device containing a control circuit with internal timing which enables it to independently adjust the timing of an interrupt acknowledge cycle. The circuit senses a timing signal from the CPU and asserts a control signal to suspend the operation of the CPU for a predetermined period of time. The predetermined period of time is customized to the peripheral so that when the CPU is re-activated and reads from the bus, a valid interrupt vector will have been put out by the peripheral.

Device for timing interrupt acknowledge cycles

A universal bus interface compatible with a number of different bus interface protocols is disclosed. In any given application, the control lines carrying signals by a processor are connected to the appropriate interface signal pins of the bus interface with all unused interface signal pins tied to their inactive level. The bus interface derives a strobe signal from the timing information carried by the control lines from the processor. The strobe signal derived by the interface controls data flow within a peripheral device or data flow between a peripheral device and a processor without the aid of any clock signals. A NAND-gate is used in the interface to derive the strobe signal from processor control signals. The NAND-gate comprises a number of inverters arranged in parallel each located close to an interface input pin to eliminate the need for any logic for driving the gate. The outputs of the inverters are connected to a common node to provide the strobe signal. When the output of an inverter falls from high to low, a feedback loop causes the output of the inverter to be in a high impedance state so that the low state of the output of such inverter does not prevent the NAND-gate output from being pulled to the high state by the output of a different inverter.

Universal bus interface

The testing circuit for testing internal nodes of a device includes storage for storing the test addresses of selected internal nodes in the device. A decoder responds to a test command from a microprocessor for selecting the test addresses from the storage and supplies the test addresses to an address bus in place of other addresses supplied to the address bus. A test decoder responds only to the test addresses on the address bus for enabling the transfer of data between the selected internal nodes in the data bus for testing the selected internal nodes.

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Los Gatos, CA, United States of America

Don Smith